TI Davinci Audio Source Codes

• TI Davinci audio driver source codes; including PCM encode and play; 
• DM6467 aic32 codec codes; including McASP driver.

When setting up EDMA for audio coding, TC0 should be used for both McASP receive/transmit to have high priority low bandwidth transfers like audio.

x265 Development - An Open Source HEVC / H.265

Hopefully x265 will like x264, which has been the best open source implementation of H.264. One of x264 pioneers, Min Chen, started the x265 project to push open source development for HEVC / H.265. His goal targets for embedded system, FPGA, GPU, and multi-cores system. We are looking forward to it. 


HEVC or H.265 (nickname) is targeted at next-generation HDTV displays and content capture systems which feature progressive scanned frame rates and display resolutions from QVGA (320x240) up to 1080p and Ultra HDTV (7680x4320), as well as improved picture quality in terms of noise level, color gamut and dynamic range. The performance goal is that HEVC should provide 2x better video compression performance than AVC (H.264) high profile, at the expense of increased computational complexity (so hardware implementations would be important). HEVC will significantly reduce bandwidth requirements  with comparable image quality  for video conferencing and streaming.

DM6467 PCI Interrupt Handling

According to "PCI Interrupt Handling on DM6467/DM6467T PCI Host", DM6467/DM6467T devices do not have PCI interrupts input lines (INTA, INTB, INTC, INTD). Thus the default EVMs cannot receive PCI interrupts from targets connected over the bus and in turn, cannot interrupt DM6467 ARM on the same. This can be worked around by using GPIO lines to receive PCI interrupts from the PCI slot to which DM6467 PCI Host EVM is connected. This requires using wires to get the INTA...D lines from the slot and connect them to DM6467 GPIO lines and modify the Host Controller driver accordingly.

Hardware Modifications

Use wires to connect PCI interrupt lines from target device(s) from respective slots to DM6467 PCI Host's GPIO pins. Following figures show 2 of the possible arrangements when using 4 target devices:

Software Modifications

In arch/arm/mach-davinci/board-dm646x-evm.c:

/* Setup DM6467 for PCI mode. In case of default EVM, the CPLD along with FET
 * switches takes care of switching to PCI Boot mode when the EVM is put in
 * the PCI slot and this funtion needs to do nothing. While in case when the
 * CPLD code/ Hardware is reworked (not to do autoswitch), the code below
 * handles mux configurations to switch to PCI (Host) mode  and takes care of
 * driving RST# over PCI Bus.
 *
 * Note: This function relies on h/w setting of PCIEN to distinguish between
 * modified and unmodified EVM and might not work in case s/w (e.g., bootloader)
 * is manipulating PCIEN after booting.
 */
static void dm646xevm_pci_setup(void)
{
 void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);

 /* Skip this if PCIEN is already set in  PINMUX0 */
 if (!((__raw_readl(base + PINMUX0)) & (1<<2))) {
  /* Power up the I/O cells for PCI interface */
  __raw_writel(__raw_readl(base + DM64XX_VDD3P3V_PWDN)
    & ~(3<<16), base + DM64XX_VDD3P3V_PWDN);

  davinci_cfg_reg(DM646X_HPI32EN);

  /* Drive GPIO[13] High to avoid reset when PCI is
   * enabled
   */
  if (gpio_request(13, "RST#") != 0) {
   pr_err("Request for GPIO13 failed.\n");
   return;
  }

  gpio_direction_output(13, 1);

  /* Ensure AUDCK1 is disabled to control GPIO[2] */
  davinci_cfg_reg(DM646X_AUDCK1);

  davinci_cfg_reg(DM646X_PCIEN);

  /* Drive GPIO[2] high to take the PCI bus out of reset
   * (drive RST#) and select B2 of the FET mux on EVM to
   * deselect NAND and switch to PCI Bus
   */
  if (gpio_request(2, "PCIRST#") != 0) {
   pr_err("Request for GPIO2 failed.\n");
   return;
  }
  gpio_direction_output(2, 1);
 } else {
  pr_info("PCI_EN is already asserted.\n");
 }
}

Pinmux Switching from NAND to PCI

static void board_init(void)

 {

   #define REG_PINMUX0 __REG(0x01C40000)

   #define REG_GPIO_DIR01 __REG(0x01C67010)

   #define REG_GPIO_OUT_DATA01 __REG(0x01C67014)

   /* Setup PSCs for Required Components */

   board_setup_psc(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_DM646X_LPSC_GPIO, 1);

   board_setup_psc(DAVINCI_GPSC_ARMDOMAIN, DAVINCI_DM646X_LPSC_PCI, 1);

   ...

   /* Set Mux Mode to GPIO */

   REG_PINMUX0 = 0x2;

    

   /* Set Direction of GPIOs to ‘OUT’ */

   REG_GPIO_DIR01 = 0x0;

     

   /* Drive GPIO[13] High */

   REG_GPIO_OUT_DATA01 = 0x2000;

    

   /* Set Mux Mode to PCI */

   REG_PINMUX0 = 0x4;

    

   /* Drive GPIO[2] High */

   REG_GPIO_OUT_DATA01 = 0x2004;

 }

DM6467 Pin Mux Utility

DM6467 PINMUX Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling all pin multiplexing functions on the DM6467.  The following peripherals have multiplexed pins: VPIF, TSIF0, TSIF1, CRGEN0, CRGEN1, EMIFA, PCI, HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin, and GPIO.

The Pin Multiplexing 0 Register controls the pin function in the EMIFA, ATA, HPI, PCI, TSIF0, TSIF1, and CRGEN.  Some muxed pins are controlled by more than one PINMUX bit field.  The Pin Multiplexing 1 Register controls the pin function in the UART0, UART1, and UART2 Blocks.

This utility allows the pin multiplexing registers of the device to be calculated with ease, as well as showing what peripherals can be used together. 

DM6467T ARM/DSP EDMA Channel Synchronization Events

The above table lists the source of EDMA synchronization events associated with each of the programmable EDMA channels (the first column) for ARM and DSP. For the DM6467T device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). See more in the following references:

1. "TMS320DM646x DMSoC Enhanced Direct Memory Access (EDMA3) Controller"

2. "TMS320DM6467T Digital Media System-on-Chip (Rev. B)" p163
3. "Reconfiguring EDMA channel allocation on ARM"

DMA channels used by DM6467 ARM and DSP

Unexpected stalling and potential deadlock condition often occur when there is a resource conflict between ARM and DSP. EDMA allocations must be carefully performed. The ARM Linux kernel source, arch/arm/mach-davinci/dm646x.c, shows the DM6447 chip specific setup including EDMA. Recent discussions "Which DMA (EDMA or QDMA) channels are used by the Codec Engine and Codec Server in DM6467T DVSDK 3.10?" and "DM6467T ARM hangs after Comm_create during instantiation of DSP codec with DVSDK 3.10 GA" in e2e.ti.com reveals some potential problems in DM6467T DVSDK 3.10, especially a EDMA hardware deadlock situation that arises when the same EDMA TC is used to perform writes to BOTH DSP SDMA (L1, L2, and HDVICP RAM/Buffers through SDMA port) AND slave memories (DDR2, EMIFA, HDVICP0/1 EDMA ports, or ARM TCM).

TMS320DM6467T Digital Media System-on-Chip (DMSoC) Silicon Revision 3.0 provided an advisory for "Unexpected Stalling and Potential Deadlock Condition When DSP L2 Memory Ports Used as RAM When L2 Memory Configured as Non-cache".

HEVC / H.265 Specification Working Draft 5 (WD5) and the HEVC Test Model 5 (HM5)

High Efficiency Video Coding (HEVC) or H.265 is the current joint video coding standardization project of ITU-T Video Coding Experts Group (ITU-T Q.6/SG 16) and ISO/IEC Moving Picture Experts Group (ISO/IEC JTC 1/SC 29/WG 11). It will further reduce by 50% the data rate needed for high quality video coding, as compared to H.264.

The 7th JCT-VC meeting (HEVC meeting) in Geneva produced three particularly important output documents: the HEVC Test Model 5 (HM5), the HEVC specification Working Draft 5 (WD5), and a document specifying common conditions and software reference configurations for HEVC coding experiments.

The meeting documents can be seen at the JCT-VC Document Register. The HEVC or H.265 Test Model 5 (HM5) is in the svn_HEVCSoftware website. More progress regarding to HEVC or H.265 may refer to the JCT-VC website.

Java Exception in thread "main" java.lang.NoClassDefFoundError

There are several Java Virtual machines and the most popular one is the Oracle Java SE. Sometime we use a remote or cloud server or run between cross platforms, even for a simple hello world Java program, we often get the "Exception in thread "main" java.lang.NoClassDefFoundError" that the class which you are trying to run was not found in the classpath, because the java.exe does not take current directory by default!  The "-cp option" may help:

java -cp "C:/Program Files/Java/jdkxxx/jre/lib;./;"

Please pay attention at the "./" at the end of the paths. See more detail in codegravity.com. 

DM6467 PCI Source Codes

• DM6467 PCI Target driver, dm646x_pci_targetdrv.c and dm646x_pci_targetdrv.h;
• DM6467 (and in some parts, EVM) specific PCI initialization,  pci-dm646x.c;
• PCI module specific types/configurations and definitions, pci.h;
• Test PCI Driver Wiki and pcidrv.c;
• Generic part of PCI Host Driver for TI PCI Module, pci-generic.c;

For more detail info regarding to DM6467t, see the reference "TMS320DM6467T Digital Media System-on-Chip" and "TMS320DM646x DMSoC Peripheral Component Interconnect (PCI) User's Guide".

Analysis of Coding Tools in HEVC Test Model (HM 1.0) – Overview

According to "Analysis of Coding Tools in HEVC Test Model (HM 1.0) – Overview", two configurations of typical coding tools of H.265 or HEVC are suggested: High Efficiency and Low Complexity, as listed in the following table.

Table 1 Structure of tools forming the high efficiency and low complexity configurations of the HM

High Efficiency	Low Complexity
Coding unit tree structure (8×8 up to 64×64 luma samples)
Prediction units
Transform unit tree structure (maximum of 3 levels)	Transform unit tree structure (maximum of 2 levels)
Transform block size of 4×4 to 32×32 samples (always square)
Angular intra prediction (maximum of 34 directions)
DCT-based interpolation filter for luma samples (1/4-sample, 12-tap)	Directional interpolation filter for luma samples (1/4-sample, 6-tap)
Bi-linear interpolation filter for chroma samples (1/8-sample)
Advanced motion vector prediction
Context adaptive binary arithmetic entropy coding	Low complexity entropy coding phase 2
Internal bit-depth increase (4 bits)	N/A
N/A	Transform precision extension (4 bits)
Deblocking filter
Adaptive loop filter	N/A

The following figure shows the framework of HEVC test model (HM) decoder. The yellow, blue and white boxes indicates the building blocks for only high efficiency configuration,  only low complexity configuration, and both configurations, respectively.

H.265 Development - thevc Tiny HEVC Baseline codec

A small group is developing thevc, Tiny HEVC Baseline codec. It is led by a x264 pioneer,chenm001. The development project is in github.

Installing and Configuring SVNServe and TortoiseSVN on Windows

When we set up a SVN repository at our local machine using tortoisesvn, we often encounter the problems of "Can't connect to host localhost". This is because unless explicitly stated, svnserve will listen for IPv6 connections where the IPv6 protocol is supported, which is true of Windows Vista, 7 and Server 2008. In order to get TortoiseSVN connecting properly, you need to set up the svnserve service as follows (from an Admin command prompt, assuming your binaries are installed at C:\SVN):

sc create svnserve binpath= "C:\Program Files\Subversion\bin\svnserve.exe --service --root C:\SVN --listen-host 0.0.0.0" displayname= "Subversion" depend= tcpip start= auto


The important bit being the --listen-host 0.0.0.0, which tells svnserve to listen for IPv4 connections. Now start your service:

net start svnserve

And when you open up svn://localhost in your repo-browser everything should be working perfectly.

See detail at http://www.renaissance-design.net.

DM6467 ARM EDMA Configuration

It is feasible to use simple DM6467 EDMA Programming on the ARM side, but EDMA channels, ownPaRAMSets, and Tccs on ARM (Region 0) should not conflict with the ones on DSP side (Region 1). A good detail info can be seen in "Reconfiguring EDMA channel allocation on ARM" for DM646x.

Multi-core System Programming and Cache Management

In a multi-core system, resource and cache management is very important since potential resource and cache contention may cause unexpected behaviors such as crashes and performance degradation. The following links provide good references:

• TI Multicore Programming Guide
• TI DaVinci and OMAP Multi-core System Cache Management; Very good guidance for DM6467 / DM8168 and OMAP system.
• Multicore Resource Management
• Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems
• Operating System-Level On-Chip Resource Management in The Multicore Era
• Dynamic Cache Contention Detection in Multi-threaded Applications

Android Building the JNI Source Code in Eclipse

Building the JNI Source Code in Eclipse is a very good tutorial to explain the steps to build JNI source code in Eclipse. I tried the NDK r6b and "Using NDK to Call C code from Android Apps" and got a successful application build.

One Click Rooting for Eee Pad Transformer TF101 8.6.6.19

Recently Asus updated it new Eee Pad Transformer TF101 firmware  8.6.6.19. Razorclaw is a new APK tool (on-device!) for rooting any version ASUS Transformer including 8.6.6.19. It is easy and cool. The current version is 1.0.1.

Install a Native C Executable on Eee Pad Transformer Android 3.2

After Eee Pad Transformer TF101 is rooted, we may like to install a native C executable which was generated by the NDK tool chain. A Busybox installer may be helpful since it provides the "cp" command. Then we may want to put this executable in /system. No matter we use "mv" or "cp", we still often get a "cross device link ERROR" or since /system is not writable unless we use something like this:

mount -o rw,remount -t yaffs2 /dev/block/mmcblk0p1 /system

If the /system is not in mmcblock0p1, please use "mount" to find the right place.

Now we can use "cp" the executable to /system/xbin, and "chmod 744 ..." to be executable.

Performance and Complexity Comparison between H.265/HEVC and H.264

HEVC Test Model under Consideration (TMuC) serves as a starting point for definition of the new video coding standard. The current version is HM-4.1-dev.

An article "Towards high efficiency video coding: Subjective evaluation of potential coding technologies" pointed out:

"The TMuC has similarities to the H.264/MPEG-4 AVC standard, including block-based intra / inter prediction, block transform and entropy coding. New features include increased prediction flexibility, more sophisticated interpolation filters, a wider range of block sizes and new entropy coding schemes. Twice the compression efficiency of H.264/MPEG-4 AVC is expected to be achieved, at the expense of a considerable increase in computational complexity. The performance of the coding algorithm resulting from this integration step will be analyzed by means of formal subjective quality assessment in a next subjective test campaign."

The article "High Performance, Low Complexity Video Coding and the Emerging HEVC Standard" describes a low complexity video codec with high coding efficiency. It was proposed to the high efficiency video coding (HEVC) standardization effort of moving picture experts group and video coding experts group, and has been partially adopted into the initial HEVC test model under consideration design. The proposal utilizes a quadtree-based coding structure with support for macroblocks of size 64 × 64, 32 × 32, and 16 × 16 pixels.

• Entropy coding is performed using a low complexity variable length coding scheme with improved context adaptation compared to the context adaptive variable length coding design in H.264/AVC. 
• The proposal's interpolation and deblocking filter designs improve coding efficiency, yet have low complexity. 

Dan Grois also summarized

• Average interpolation complexity is less than that of H.264/AVC due to the 1-D directional interpolation filters. 
• Memory bandwidth for motion compensation is lower than H.264/AVC. This is because motion partitions smaller than 8 × 8 are not used. 
• Interpolation complexity for B pictures is significantly lower in the proposal than in H.264/AVC, as the SKIP and DIRECT modes use integer motion vectors. Using motion vectors with integer pixel accuracy implies that reconstruction of a SKIP/DIRECT block can be done by copying pixels from one location in memory to another location, instead of applying the 6-tap interpolation filter. 
• The deblocking filter has significantly lower computational complexity. This is mainly because a much lower number of block edges are filtered, and the filter has simpler logic for enabling/disabling the filter on an edge. In addition, filtering can be performed in parallel first for each of the vertical edges and then for each of the horizontal edges, which is not possible for H.264/AVC. 
• VLC (de)coding of coefficients is simpler than H.264/AVC CAVLC coefficient (de)coding. In particular, CAVLC relies on decoding a large number of syntax elements (e.g., coeff−token, trailing−ones−sign−flag, level−prefix, level−suffix, total−zeros, and run−before). Also, the VLC decoding uses significantly fewer syntax elements, and requires less conditional branches (run/level/sign in run mode, and level/sign in level mode). 

Samuelsson at el. proposed a method to for "Simplification of Intra Prediction Mode" for HEVC. The result shows that this processing is adaptive to the content of the video, and results in a reduction in the computational complexity of the prediction process by approximately 50%.

Using NDK to Call C code from Android Apps

Android NDK (Native Development Kit) allows working with native C code using a shared C library. It includes the entire toolchain needed to build for your target platform (ARM). Native C code accessible via JNI still runs inside the Dalvik VM, and as such is subject to the same life-cycle rules that any Android application lives by. The advantage of writing parts of your app code in native language is presumably speed in certain cases.



See more at Marko Gargenta's article.

DM8168 EVM for $999

Spectrum Digital is now shipping the DM816x/C6A816x/AM389x Standalone EVM Baseboard. This is the processor board which makes up part of the full development kit offered by TI. This CPU module allows developers to get additional platforms in a cost effective manner for software developers.This module, # 702391, is being offered in North America at a quantity one price of $999.00.

DM6467 ARM9 Trouble Writing Memory Block at 0x1c40900

When connecting to DM6467 from CCS (3.3.82.13), using XDS510PP Plus (Rev A) and the DM6467t Gel file from Spectrumdigital, we may see

"Trouble Writing Memory Block at 0x1c40900 on Page 0 of Length 0x4: Error 0x80002002/..."

The problem is due to "It is possible that when PLL is being programmed you loose RTCK while PLL is switching over.  The RTCK will also become much slower as it is slaved to the device core clock. It may only work if you are using an external adaptive clocking adapter to deal the RTCK issue. Aside of this, you will need to configure the PP+ via SdConfig(Ex) to uncheck disable polling and set the port speed to 100.  This will force the emulator to poll for emulator command completion and the 100 is the max retry loop count. " The fix is as follows.

Qualcomm to Lose HTC to Nvidia Tegra 3?

Like in recently announced Eee Pad Transformer Prime, the first tablet to feature Nvidia's new Tegra 3 quad-core processor, has attracted attention, Tegra 3 quad-core processor seems that it will be adapted by more phones and tablet. Desire Athow wrote:

HTC will apparently break the exclusivity of Qualcomm by adopting the penta-core Nvidia Tegra 3 chipset to power a new handset, the Edge, that is set to be launched next year at MWC.

According to Monica Chen and Joseph Tsai from Digitimes, the phone will launch either in March or April and will come with Nvidia's chipset, which would be a blow to Qualcomm who may lose both HTC and Sony Ericsson as exclusive partners in a single year. 

In addition, Microsoft has also confirmed that ST-Ericsson will also start producing chips for Windows Phone handsets ,heralding the end of the monopoly Qualcomm had on the platform.

Samsung Electronics, Motorola and LG have also adopted the Tegra 3 for their handsets and Asus has already shipped the first tablet based on the chipset , the Transformer Prime.

The new Tegra 3 adopts a similar strategy as ARM's big.LITTLE or TI's OMAP4, with smaller CPU(s) taking over from big ones for mundane and light tasks.

Nvidia says that the system on chip has three times the graphics performance of its predecessor - thanks to 12 GPU cores - while consuming almost two thirds less power than the Tegra 2.

Read more: http://www.itproportal.com/2011/11/14/qualcomm-lose-htc-nvidia-tegra-3/#ixzz1dyIrkEa3

Eee Pad Transformer TF101 Android 3.2.1 Root and adb shell

1. Download Asus Transformer NVFlash Stock 3.2 Recovery Roms from tabletroms.com; The latest version is the 3.2 Build of 8.6.5.13 which is the same as the one in Asus website;
2. NV flash the ROM with following the instruction in tabletroms.com;
3. Download Universal root toolkit v7.1 from xda-developers.com;
4. Backup and root it;
5. If "adb devices" returns nothing, you may unplug the USB cable and try to update the device driver using the USB driver in the transformer 3.1 rootkit.  If sometime SU can't not be installed due to ADB path problem, may also try the transformer 3.1 rootkit. However, if your adb path is set in the Windows environment, you may also need to delete the adb.exe in the tool kit;
6. Use Root Check Pro to check if the transformer is rooted.

HTML5 and Adobe Flash's Failures

Since Apple refused to accept Flash and Windows 8 Phone and tablet will not support Flash, and Adobe want to focus on HTML5 development, Adobe abandons mobile Flash development.

Flash Video is a container file format used to deliver video over the Internet using Adobe Flash Player versions 6–11. Flash Video content may also be embedded within SWF files. There are two different video file formats known as Flash Video: FLV and F4V. The audio and video data within FLV files are encoded in the same way as they are within SWF files. Flash Video FLV files usually contain material encoded with codecs following VP6 video compression formats. The most recent public releases of Flash Player also support H.264 video and HE-AAC audio.

Today David Murphy reported "Who's to Blame for Adobe Flash's Failures?" in pcmag.com. In his report, he referred to Cera Technology CEO Michael Mace's words "The root causes of the Flash failure should blame to a fundamental misreading of the mobile market, and to short-term revenue goals that were more important than long-term strategy at both Macromedia and Adobe. The full Flash player had been designed for PCs; it was too fat to run well on a smartphone." ...

Currently HTML5 Video Player is an opt-in trial for YouTube. It supports browsers that support both the video tag in HTML5 and either the h.264 video codec or the WebM format (with VP8 codec).

iOS 5.0.1 Update Failed

I tried to update my iPhone 3GS with iOS 5.0.1 which was released on Thursday to fix a critical security hole and promise better battery life for iPhone 4S users. It seems Apple may have not sufficiently tested it before release. Not only my update failed, but also my iPhone firmware could not be restored at the first try. I tried reset via tap both home button and power off button and a different cable, and finally got the restored firmware.

Updated: strangely enough, after I restored the firmware, my iOS is 5.0.1.

DM6467 Latest CODECS

TI published the latest DM6467 codec, DM6467_CODECS 1_00_003 Product, on October 24, 2011. However H.264 1080p encoder was not updated.

H.264 Encoder, Version 1.20.02.00 DataSheet	H264 BP/MP/HP L4.0 720p Encoder Data Sheet	648K
H.264 Encoder, Version 1.20.02.00 ReleaseNotes	H264 BP/MP/HP L4.0 720p Encoder Release Notes	128K
H.264 Encoder, Version 1.10.02.05 DataSheet	H264 BP/MP/HP L4.0 1080p Encoder Data Sheet	116K
H.264 Encoder, Version 1.10.02.05 ReleaseNotes	H264 BP/MP/HP L4.0 1080p Encoder Release Notes	48K

Transformer Prime vs. iPad 2 vs. Kindle Fire vs. Nook Tablet

There is more than enough room for tablet players. Current estimates suggest tablet sales will increase on average 83% a year to 185 million units in 2014; RBC estimates Apple will sell 50 million iPads in fiscal 2012 (up 54% yearly) and 65 million in 2013.

Asus' newly announced Eee Pad Transformer Prime, the first tablet to feature Nvidia's new Tegra 3 quad-core processor. The Prime will get an upgrade to Ice Cream Sandwich. The Prime joins Amazon's Kindle Fire and Barnes & Noble's Nook Tablet as the latest set of tablet devices hitting store shelves before the end of the year. Ian Paul, PCWorld, gave comparisons between four tablets:

Intel and MIPS Bets on Android 4.0 Ice Cream Sandwich with 2012 Release

Android 4.0 Ice Cream Sandwich includes many improvements including a new interface and system bar that makes accessing and navigating through applications easier. Other features include an improved keyboard, integration of multiple email accounts, improved security, core application improvements, and near-field communications (NFC) abilities for mobile payments. It also provides  impressive media processing features, such as face unlock, camera functions for quicker photo, live effect, enhanced Talk-to-Text, and photo editor.

It has already been shown to work on a smartphone with an ARM processor. HTC confirmed that the HTC Sensation, HTC Sensation XL, HTC Sensation XE, HTC Rezound, HTC EVO 3D, HTC EVO Design 4G, and HTC Amaze 4G would all be seeing the update to Android 4.0.

The new OS includes OS optimization for x86, so Intel architecture-based devices, can support it, according to Suzy Greenberg, an Intel spokeswoman. HP new tablet Slate 2 includes faster hardware including Intel's Atom Z670 processor, which runs at a clock speed of 1.5GHz and has accelerators to decode 1080p video. 

MIPS is the third processor architecture challenging ARM in the tablet and smartphone space. Tablets with MIPS processors already support Android 3.0, which is code-named Honeycomb, and the company is porting Android 4.0 for tablets.

See more @ computerworld.

DM6467 Boot

• The DM646x boot document "Using the TMS320DM646x DMSoC Bootloader (Rev. D)"
• davinci-psp_3.2.0.0-beta/sources
• Creating a DSP Boot Image for Host Boot
• dm646x_pci_targetdrv.c

Xilinx ISE 13.3, Artix-7 and Virtex-7 XT

This release is another try to support Artix-7 and Virtex-7 XT. According to the company press release, a full custom precision floating-point support, including new bit and cycle accurate, single, double and full custom precision floating-point in system generator for DSP, is provided to extend productivity for DSP designers.

Artix™-7 FPGAs deliver the lowest power and lowest cost to address high-volume markets. This family is one of three product families built on a common 28nm architecture designed for maximum power efficiency and offers over two times the capacity, 30% higher performance, 50% lower power consumption -- and logic up to 350K logic cell density at lower price points than Spartan®-6 FPGAs.

Virtex-7 FPGAs are optimized for advanced systems requiring the highest performance and highest bandwidth connectivity. Utilizing innovative 2.5D Stacked Silicon Interconnect (SSI) technology, 

the latest Virtex-7, 2000T FPGA, integrates 2 million logic cells, 6.8 billion transistors and 12.5Gb/s serial transceivers on a single device making it the world’s highest capacity FPGA. This is equivalent to 20 million ASIC gates.Virtex-7 XT provides larger block RAM (85.0Mb) than other Virtex-7 devices.

DM8168 or C6-Integra EVM

DM8168 is among the TI AM389x, C6A816x, DM816x Device family with multi-HD codec support.



Developed with Spectrum Digital, the DM8168 Evaluation Module (EVM) enables developers to immediately start evaluating DM816x DaVinci™ MPU (DM8168, DM8167, DM8166, DM8165), C6A816x C6-Integra™ DSP+ARM processors (C6A8168, C6A8167) and AM389x Sitara™ ARM MPUs (AM3894, AM3892) and begin building solutions such as surveillance DVRs, video conferencing systems, video broadcasting systems, media servers, single-board computers, gateways, routers, servers, industrial automation, human machine interfaces (HMIs), point-of-service data terminals, machine vision, test and measurement, tracking and control applications, amongst many others. The board contains

• with connectors for composite video, S-Video, Component Video, serial port, SD, SATA, PCIe, USB, Ethernet, Audio Input/Output, HDMI Tx
• DM8168 Processor (emulates AM3894 and C6A816)
• Expansion I/O Daughtercard (printed circuit board assembly) with connectors for DVI in, Component Video in, Composite Video in, HDMI Tx, serial port, Ethernet, and Audio outputs
• 7” Touch-screen LCD display
• Power supply and regional adapter
• Serial, USB, Ethernet and HDMI cables
• USB mouse
• SD card (with example software and SDK)
• SD card reader (for plugging in SD card to PC) JTAG emulator (XDS100)
• 1 GB DDR3 Memory

The technical reference of the EVM shows goof info. The Ubuntu based SDK 2011Q2 for DM8168 EVM Board was released in Oct 2011. Android Rowboat is supported for DM8168 platform. Android GingerBread is supported for ARM Cortex-A8 based AM389x.

TI demonstrated a bottle detection using the machine vision function in OpenCV.

Machine Vision Demo using OpenCV Machine Vision demosttration using OpenCV on Texas Instruments' C6-Integra(TM) platform Posted: 21-Apr-2011 Duration: 4:33 Views: 4535 Tags: integra, c6-integra, opencv,machine vision, c6a816x, omap-l13x C6-Integra(TM) DSP+ARM Processors

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