Wednesday, December 28, 2011

TI Davinci Audio Source Codes

When setting up EDMA for audio coding, TC0 should be used for both McASP receive/transmit to have high priority low bandwidth transfers like audio.

Tuesday, December 27, 2011

x265 Development - An Open Source HEVC / H.265

Hopefully x265 will like x264, which has been the best open source implementation of H.264. One of x264 pioneers, Min Chen, started the x265 project to push open source development for HEVC / H.265. His goal targets for embedded system, FPGA, GPU, and multi-cores system. We are looking forward to it. 

HEVC or H.265 (nickname) is targeted at next-generation HDTV displays and content capture systems which feature progressive scanned frame rates and display resolutions from QVGA (320x240) up to 1080p and Ultra HDTV (7680x4320), as well as improved picture quality in terms of noise level, color gamut and dynamic range. The performance goal is that HEVC should provide 2x better video compression performance than AVC (H.264) high profile, at the expense of increased computational complexity (so hardware implementations would be important). HEVC will significantly reduce bandwidth requirements  with comparable image quality  for video conferencing and streaming.

Sunday, December 25, 2011

DM6467 PCI Interrupt Handling

According to "PCI Interrupt Handling on DM6467/DM6467T PCI Host", DM6467/DM6467T devices do not have PCI interrupts input lines (INTA, INTB, INTC, INTD). Thus the default EVMs cannot receive PCI interrupts from targets connected over the bus and in turn, cannot interrupt DM6467 ARM on the same. This can be worked around by using GPIO lines to receive PCI interrupts from the PCI slot to which DM6467 PCI Host EVM is connected. This requires using wires to get the INTA...D lines from the slot and connect them to DM6467 GPIO lines and modify the Host Controller driver accordingly.

Hardware Modifications

Use wires to connect PCI interrupt lines from target device(s) from respective slots to DM6467 PCI Host's GPIO pins. Following figures show 2 of the possible arrangements when using 4 target devices:

Software Modifications

/* Setup DM6467 for PCI mode. In case of default EVM, the CPLD along with FET
 * switches takes care of switching to PCI Boot mode when the EVM is put in
 * the PCI slot and this funtion needs to do nothing. While in case when the
 * CPLD code/ Hardware is reworked (not to do autoswitch), the code below
 * handles mux configurations to switch to PCI (Host) mode  and takes care of
 * driving RST# over PCI Bus.
 * Note: This function relies on h/w setting of PCIEN to distinguish between
 * modified and unmodified EVM and might not work in case s/w (e.g., bootloader)
 * is manipulating PCIEN after booting.
static void dm646xevm_pci_setup(void)

 /* Skip this if PCIEN is already set in  PINMUX0 */
 if (!((__raw_readl(base + PINMUX0)) & (1<<2))) {
  /* Power up the I/O cells for PCI interface */
  __raw_writel(__raw_readl(base + DM64XX_VDD3P3V_PWDN)
    & ~(3<<16), base + DM64XX_VDD3P3V_PWDN);


  /* Drive GPIO[13] High to avoid reset when PCI is
   * enabled
  if (gpio_request(13, "RST#") != 0) {
   pr_err("Request for GPIO13 failed.\n");

  gpio_direction_output(13, 1);

  /* Ensure AUDCK1 is disabled to control GPIO[2] */


  /* Drive GPIO[2] high to take the PCI bus out of reset
   * (drive RST#) and select B2 of the FET mux on EVM to
   * deselect NAND and switch to PCI Bus
  if (gpio_request(2, "PCIRST#") != 0) {
   pr_err("Request for GPIO2 failed.\n");
  gpio_direction_output(2, 1);
 } else {
  pr_info("PCI_EN is already asserted.\n");

Pinmux Switching from NAND to PCI

static void board_init(void)
   #define REG_PINMUX0 __REG(0x01C40000)
   #define REG_GPIO_DIR01 __REG(0x01C67010)
   #define REG_GPIO_OUT_DATA01 __REG(0x01C67014)
   /* Setup PSCs for Required Components */
   /* Set Mux Mode to GPIO */
   REG_PINMUX0 = 0x2;
   /* Set Direction of GPIOs to ‘OUT’ */
   REG_GPIO_DIR01 = 0x0;
   /* Drive GPIO[13] High */
   REG_GPIO_OUT_DATA01 = 0x2000;
   /* Set Mux Mode to PCI */
   REG_PINMUX0 = 0x4;
   /* Drive GPIO[2] High */
   REG_GPIO_OUT_DATA01 = 0x2004;

DM6467 PINMUX Registers PINMUX0 and PINMUX1 in the System Module are responsible for controlling all pin multiplexing functions on the DM6467.  The following peripherals have multiplexed pins: VPIF, TSIF0, TSIF1, CRGEN0, CRGEN1, EMIFA, PCI, HPI, ATA, PWM0, PWM1, UART0, UART1, UART2, Audio Clock Selector, the USB USB_DRVVBUS pin, and GPIO.

The Pin Multiplexing 0 Register controls the pin function in the EMIFA, ATA, HPI, PCI, TSIF0, TSIF1, and CRGEN.  Some muxed pins are controlled by more than one PINMUX bit field.  The Pin Multiplexing 1 Register controls the pin function in the UART0, UART1, and UART2 Blocks.

This utility allows the pin multiplexing registers of the device to be calculated with ease, as well as showing what peripherals can be used together. 

Saturday, December 24, 2011

DM6467T ARM/DSP EDMA Channel Synchronization Events

The above table lists the source of EDMA synchronization events associated with each of the programmable EDMA channels (the first column) for ARM and DSP. For the DM6467T device, the association of an event to a channel is fixed; each of the EDMA channels has one specific event associated with it. These specific events are captured in the EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). See more in the following references:

Friday, December 23, 2011

DMA channels used by DM6467 ARM and DSP

Unexpected stalling and potential deadlock condition often occur when there is a resource conflict between ARM and DSP. EDMA allocations must be carefully performed. The ARM Linux kernel source, arch/arm/mach-davinci/dm646x.c, shows the DM6447 chip specific setup including EDMA. Recent discussions "Which DMA (EDMA or QDMA) channels are used by the Codec Engine and Codec Server in DM6467T DVSDK 3.10?" and "DM6467T ARM hangs after Comm_create during instantiation of DSP codec with DVSDK 3.10 GA" in reveals some potential problems in DM6467T DVSDK 3.10, especially a EDMA hardware deadlock situation that arises when the same EDMA TC is used to perform writes to BOTH DSP SDMA (L1, L2, and HDVICP RAM/Buffers through SDMA port) AND slave memories (DDR2, EMIFA, HDVICP0/1 EDMA ports, or ARM TCM).

TMS320DM6467T Digital Media System-on-Chip (DMSoC) Silicon Revision 3.0 provided an advisory for "Unexpected Stalling and Potential Deadlock Condition When DSP L2 Memory Ports Used as RAM When L2 Memory Configured as Non-cache".

Tuesday, December 20, 2011

HEVC / H.265 Specification Working Draft 5 (WD5) and the HEVC Test Model 5 (HM5)

High Efficiency Video Coding (HEVC) or H.265 is the current joint video coding standardization project of ITU-T Video Coding Experts Group (ITU-T Q.6/SG 16) and ISO/IEC Moving Picture Experts Group (ISO/IEC JTC 1/SC 29/WG 11). It will further reduce by 50% the data rate needed for high quality video coding, as compared to H.264.

The 7th JCT-VC meeting (HEVC meeting) in Geneva produced three particularly important output documents: the HEVC Test Model 5 (HM5), the HEVC specification Working Draft 5 (WD5), and a document specifying common conditions and software reference configurations for HEVC coding experiments.

The meeting documents can be seen at the JCT-VC Document Register. The HEVC or H.265 Test Model 5 (HM5) is in the svn_HEVCSoftware website. More progress regarding to HEVC or H.265 may refer to the JCT-VC website.

Saturday, December 17, 2011

Java Exception in thread "main" java.lang.NoClassDefFoundError

There are several Java Virtual machines and the most popular one is the Oracle Java SE. Sometime we use a remote or cloud server or run between cross platforms, even for a simple hello world Java program, we often get the "Exception in thread "main" java.lang.NoClassDefFoundError" that the class which you are trying to run was not found in the classpath, because the java.exe does not take current directory by default!  The "-cp option" may help:

java -cp "C:/Program Files/Java/jdkxxx/jre/lib;./;"

Please pay attention at the "./" at the end of the paths. See more detail in

DM6467 PCI Source Codes

Wednesday, December 14, 2011

Analysis of Coding Tools in HEVC Test Model (HM 1.0) – Overview

According to "Analysis of Coding Tools in HEVC Test Model (HM 1.0) – Overview", two configurations of typical coding tools of H.265 or HEVC are suggested: High Efficiency and Low Complexity, as listed in the following table.

Table 1 Structure of tools forming the high efficiency and low complexity configurations of the HM
High EfficiencyLow Complexity
Coding unit tree structure (8×8 up to 64×64 luma samples)
Prediction units
Transform unit tree structure (maximum of 3 levels)Transform unit tree structure (maximum of 2 levels)
Transform block size of 4×4 to 32×32 samples (always square)
Angular intra prediction (maximum of 34 directions)
DCT-based interpolation filter for luma samples (1/4-sample, 12-tap)Directional interpolation filter for luma samples (1/4-sample, 6-tap)
Bi-linear interpolation filter for chroma samples (1/8-sample)
Advanced motion vector prediction
Context adaptive binary arithmetic entropy codingLow complexity entropy coding phase 2
Internal bit-depth increase (4 bits)N/A
N/ATransform precision extension (4 bits)
Deblocking filter
Adaptive loop filterN/A

The following figure shows the framework of HEVC test model (HM) decoder. The yellow, blue and white boxes indicates the building blocks for only high efficiency configuration,  only low complexity configuration, and both configurations, respectively.
HM Decoder

H.265 Development - thevc Tiny HEVC Baseline codec

A small group is developing thevc, Tiny HEVC Baseline codec. It is led by a x264 pioneer,chenm001. The development project is in github.

Saturday, December 10, 2011

Installing and Configuring SVNServe and TortoiseSVN on Windows

When we set up a SVN repository at our local machine using tortoisesvn, we often encounter the problems of "Can't connect to host localhost". This is because unless explicitly stated, svnserve will listen for IPv6 connections where the IPv6 protocol is supported, which is true of Windows Vista, 7 and Server 2008. In order to get TortoiseSVN connecting properly, you need to set up the svnserve service as follows (from an Admin command prompt, assuming your binaries are installed at C:\SVN):

sc create svnserve binpath= "C:\Program Files\Subversion\bin\svnserve.exe --service --root C:\SVN --listen-host" displayname= "Subversion" depend= tcpip start= auto

The important bit being the --listen-host, which tells svnserve to listen for IPv4 connections. Now start your service:

net start svnserve

And when you open up svn://localhost in your repo-browser everything should be working perfectly.

See detail at

Thursday, December 1, 2011

DM6467 ARM EDMA Configuration

It is feasible to use simple DM6467 EDMA Programming on the ARM side, but EDMA channels, ownPaRAMSets, and Tccs on ARM (Region 0) should not conflict with the ones on DSP side (Region 1). A good detail info can be seen in "Reconfiguring EDMA channel allocation on ARM" for DM646x.

Multi-core System Programming and Cache Management

In a multi-core system, resource and cache management is very important since potential resource and cache contention may cause unexpected behaviors such as crashes and performance degradation. The following links provide good references:


Blog Archive

About Me

My photo
HD Multimedia Technology player