Tuesday, June 29, 2010



BDTI report:

BDT’s conclusion is that they “were impressed with the quality of results that AutoPilot was able to produce given that this has been a historic weakness for HLS tools in general.” The only real negative is that the tool chain is more expensive (since AutoESL doesn’t come bundled with your FPGA or your DSP).

EDA review:

AutoESL provides a powerful high level synthesis solution that enables:

  • Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs
  • Software architects to accelerate software algorithms by implementing them in silicon
  • System architects to take software models into silicon without manually writing RTL
  • Hardware architects to explore and implement the right architecture in silicon

AutoPilot™ is the industry's only high level synthesis solution that:

  • Provides broadest multi-language support for C, C++ and SystemC
  • Delivers QoR equal to or better than hand-coded RTL
  • Optimally targets both ASICs and FPGAs
  • Is suited for multiple application domains such as video, wireless, networking, accelerated computing and DSP

Overview of the Technology

  • Platform-based communication-centric synthesis
  • Unified coverage of C,C++, and SystemC languages
  • Advanced code transformations
  • Highly scalable ESL optimization
  • Direct synthesis of single and double precision floating point operations
  • Black-box Xilinx FPGA core support
  • Automatic RTL test bench generation
  • Industry standard Eclipse user interface
  • Generates synthesizable VHDL, Verilog HDL, and SystemC code

Thursday, June 24, 2010

HDMI 1.3 Interface FPGA Mezzanine Card (FMC)



HDMI 1.3 Interface FPGA Mezzanine Card (FMC)


  • HDMI 1.3 Encoder (Non-HDCP)
  • HDMI 1.3 Decoder (Non-HDCP)
  • FMC Low Pin Count connector w/ RGB (10-bit) + HSync + VSync + Data Enable interfaces (RX && TX) to carrier card
  • Power supplied either by external supply or through FMC connector +12V and +3.3V from carrier card
  • UART Interface
  • I2C EEPROM Interface
  • JTAG Interface for programming the Spartan 3AN
  • Selectable encoder HSYNC, VSYNC polarity levels (both normal, both inverted)

    Key Components




    inrevium TB-FMCL-HDMI FPGA Mezzanine Card
    inrevium TB-FMCL-HDMI FPGA Mezzanine Card (click to enlarge)
    Buy from Aspen Logic
    (lead time 2 weeks)

    Xilinx ChipScope Tutorial

    The official document 12.1 is


    But the following tutorials are helpful:


    Tutorial 11 gives an introduction to Chipscope. The reader will learn how to implement a Chipscope core in their design. Chipscope is a valuable tool that provides digital designers a logic analyzer within the FPGA. The tutorial uses Xilinx ISE 10.1, Chipscope and the Spartan-3E starter board.

    Some other tutorials can be found in

    PlanAhead Software Tutorial with Chipscope is in

    Wednesday, June 23, 2010

    Spartan-6 High Speed Serial IO Evaluation Platform


    Target Applications Include: Consumer Display, AVB, Medical


    • 8 GTP connections over the HPC
    • FMC LPC connector x3, HPC connector x1
    • 2x 2 GBit DDR2 SDRAM, x16-bit @ 800 Mbps
    • Dip switch x8, Push button x4, User LED x8
    • MMCX Differential Clock Inputs (P & N)
    • MMCX Singled ended clock output

    Key Components

    • Spartan-6 LX150T (XC6SLX150T-2FGG676)
    • DDR2 SDRAM (EDE2116ACBG)
    • FMC LPC connector (ASP-134603-01)
    • FMC HPC connector (ASP-134486-01)
    • SPI Flash (M25P64-VMF6)
    • 74.25MHz oscillator
    • Optional oscillator socket
    • Clock driver (ICS8545AG-02LF)
    • MMCX Single ended clock input
    • Clock Cleaner PLL (ICS8100001DK-21LF) and clock distribution driver (ICS8545AG-02LF) to FMC HPC
    • 135 MHz oscillator and clock distribution driver (ICS8543BGLF) to FMC HPC
    • Reset IC (LTC1326CMSB)
    • RS232C-to-USB (FT232BL) with USB Connector (B Type)




    Logic Design


      Reference Designs

      • DDR2 SDRAM Reference Design
      TB-6S-LX150T-IMG Front Side (Click to enlarge)
      TB-6S-LX150T-IMG Front Side Image (Click to Enlarge)
      Buy From Aspen Logic
      (2 week lead time)
      $995 (Does not include any FMCs)

      Comparison Between VP8 and H.264 (3): VP8 vs x264


      Some interesting results of encoding 720p videos with VP8 and x264 were shown using different settings and bitrate and qpsnr to compute the PSNR and SSIM of the videos themselves. The conclusions are as follows.

      "What can I say?
      Well, given that in many occasions PSNR and SSIM aren't far away between x264 and VP8, VP8 is a fair competitor for x264.
      Indeed, currently (Jun 2010) the badly implemented VP8 encoder (--best option in ivfenc) offers same quality as x264 normal. Which is pretty good considering the fact that there's room for improvement.
      Would I use VP8 now to save my HD videos? Not really, because ffmpeg 0.6 is extremely slow (6+ FPS on my 4 cores AMD x4 965 B.E.), and doesn't use all of my 4 cores, while Handbrake is faster ( 60+ FPS) and uses 4 corse 100% each. And even if ivfenc is faster than ffmpeg there is still the question about playing videos on other devices which at the moment don't support VP8.
      So, from my viewpoint, VP8 is not usable in production right now, but once it'll be better implemented (and maybe the encoder will manage to better save background details) VP8, given the patent free nature of this format, could become the real standard.

      • Compression speed: in this case the real winner is x264; VP8 code needs much more improvement to be comptetitive (at least using ffmpeg, ivfenc needs improvements as well).
      • Patents and royalties: well clearly VP8 is the winner here, without chance for x264 to ever come near. Unless MPEG L.A. decides to make it become a royalty free standard (which I definitely doubt as seen as they make money out of patents).
      • Quality: they are sort of tied now, x264 is slightly better in more static scenes while VP8 is better for highly dynamic ones. But when proper encoders will be available for VP8 probably we'll see it fill (at least some) the gap in less dynamic scenes.
      • Hardware accelleration: this was one of the major publicity stun that was lacking for other video formats than x264 (h.264 to be specific). But now a lot of companies have announced hardware support for VP8.

      Final words
      At the moment x264 is having the edge because is a very good encoder, stable since some years and really implements the h.264 standard inside out. In a nice way indeed.
      VP8 is like rough gold, it needs to be primed, in the code and perhaps some details algorithm search as well.
      But give VP8 some time, I feel that this one could be a real liberation (and evolution if I may say) from a heavily patented codec.

      If you want to have a word, please contact me at ema at _fast_web_net.it (remove the _ otherwise email address won't work)."

      Tuesday, June 22, 2010

      Xilinx 28nm New 7 Series FPGAs


      Xilinx, Inc. yesterday announced the industry's first FPGA series that slashes total power consumption by 50 percent and offers industry-leading capacity of up to 2 million logic cells on the only unified architecture that scales across low-cost to ultra high-end families. Xilinx 7 series FPGAs further extend the range of applications programmable logic can address by breaking new ground in solving customer challenges for lower power and cost without compromising on higher capacity and increased performance. Implemented on 28-nanometer (nm) process technology optimized to deliver low power with high performance, the new families enable significant levels of productivity as skyrocketing development costs, complexity, and inflexibility of alternative ASIC and ASSP technology make FPGA platforms more relevant to an increasingly diverse community of designers.

      The 28nm families extend Xilinx's Targeted Design Platform strategy introduced with the company's 40nm Virtex®-6 and 45nm Spartan®-6 FPGA families, now in volume production. The Targeted Design Platform strategy combines FPGAs, ISE® Design Suite software tools and IP, development kits, and targeted reference designs to enable customers to leverage their existing design investments and reduce their overall costs as they meet evolving market needs. In this new generation, Xilinx also takes a critical next step in its work to dramatically expand the ecosystem of available IP and designs that enable customers to focus on differentiation even as they transition to 28nm devices.

      "The 7 series represents a new juncture for Xilinx, and the FPGA industry in general, as we bring our technology portfolio to new markets by putting a significant emphasis on lowering power consumption," said Xilinx President and CEO Moshe Gavrielov. "In addition to delivering what we and our customers expect from Moore's Law in terms of capacity and performance with each new generation, we continue our focus on opening programmable logic to a broader audience by delivering design platforms targeted toward the specific needs of new users and markets."

      • Virtex-7 Family: Delivering a 2X system performance improvement at 50 percent lower power compared to Virtex-6 devices, the ultra high-end Virtex-7 family sets new industry benchmarks with 1.8X greater signal processing performance, 1.6x greater I/O bandwidth, 2X greater memory bandwidth with 2133 Mbps memory interfacing performance, and delivers the industry's largest density FPGA with 2 million logic cells, which is 2.5X greater density than any previous or existing FPGA. EasyPath-7 devices are also available for all Virtex-7 FPGAs for a guaranteed 35% cost reduction without requiring any design conversion. Virtex-7 devices enable 400G bridging and switch fabric wired communication systems that are at the heart of the global wired infrastructure, advance RADAR systems, and high-performance computer systems that require single-chip TeraMACC signal processing capabilities, as well as the logic density, performance, and I/O bandwidth required for next generation test and measurement equipment. The Virtex-7 family will include "XT" extended capability devices with as many as 80 transceivers supporting individual line rates up to 13.1Gbps and devices that provide up to 1.9Tbps serial bandwidth. Also, these devices offer up to 850 SelectIO pins enabling the industry's greatest number of parallel banks of 72-bit DDR3 memory interfaces supporting 2133Mbps. Future devices will also feature 28Gbps transceivers.
      • Kintex-7 Family: Establishing a new category of FPGAs, the Kintex-7 family delivers Virtex-6 family performance at less than half the price for a 2x price/performance improvement while consuming 50 percent less power. The family includes high-performance 10.3Gbps or lower-cost optimized 6.5Gbps serial connectivity, memory, and logic performance required for applications such as high volume 10G optical wired communication equipment. It also provides a balance of signal processing performance, power consumption, and cost to support the deployment of Long Term Evolution (LTE) wireless networks, meet the aggressive power and cost requirements required for next generation high definition 3D flat panel displays, and deliver the performance and bandwidth needed for next generation broadcast video-on-demand systems.
      • Artix-7 Family: Delivering 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family, the Artix-7 family utilizes small form-factor packaging and the unified Virtex-series based architecture to deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs. This new family meets low power performance requirements of battery-powered portable ultrasound equipment, and addresses small form factor, low power requirements for commercial digital camera lens control, as well as the strict size, weight, power, and cost (SWAPc) requirements for military avionics and communications equipment.

      Sunday, June 20, 2010

      Synphony C Compiler

      As the result of acquisition of Synfora, now Synopsys provides a C Compiler for FPGA and ASIC development, currently mainly focus on prototyping. It is competing directly with Mentor's
      CatapultC, Forte's Cynthesizer, and Cadence's C-to-Silicon tools:

      High Level Synthesis with Synphony C Compiler
      Delivering the Lowest Power hardware for Mobile and Consumer Devices

      Design teams are under growing pressure to create faster, cheaper, better products. Increasingly power consumption is becoming the most critical differentiator, and designers struggle to indentify where power is being consumed and how to reduce the power consumption. Synphony C Compiler is the industry’s first algorithmic synthesis tool that automatically optimizes the power consumption at the system level using a variety of techniques including automatic multi-level clock gating insertion along with the necessary control logic. Synphony C Compiler has delivered savings of up to 50% using this technique.

      About Synphony C Compiler
      Synopsys's Synphony C Compiler creates application accelerators from sequential, untimed C algorithms for complex processing hardware in video, imaging, wireless and security domains. Synphony generates RTL, verification test-benches, SystemC models at multiple levels of accuracy, software driver and interoperability scripts.

      Synphony C Compiler delivers high productivity gains by creating application accelerators from high level C/C++ code and automating the verification down through implementation. Synphony C Compiler achieves excellent QoR through a unique parallelizing compiler, using multi-level hierarchical abstraction and IP reuse.

      Synphony C Compiler
      Synphony C Compiler introduces a major innovation in algorithmic synthesis -- automatic multi-level clock gating insertion – to enable power optimizations at the system level and eliminate all manual work. In traditional RTL (Register Transfer Language) design methodologies, inserting clock gating at a block level is usually a manual effort because it requires the knowledge of when the block is inactive. Using Synphony C Compiler, the designer uses directives to specify where to insert clock gating, and Synphony does the rest automatically. In all cases the user can make changes without having to impact the algorithm or the code.

      As a result, Synphony C Compiler allows designers to retain all the productivity benefits of automated synthesis and verification, including reduced design and verification time and the ability to react very rapidly to changes in the design specification, while optimizing the IC power consumption.

      Key Capabilities

      Coarse-Grain Clock Gating:
      Synphony C Compiler builds the clock gating infrastructure to turn off complete blocks at the top level of the design; for example, to turn off the complete quantize stage of an imaging pipeline. Of critical value is the control logic that will indicate when the block can be turned off. Synphony C Compiler understands exactly when every block is active versus idle, so the clock enable logic can be designed automatically. There is no need for time consuming manual analysis to decide “when” a block can be turned off.

      Fine-Grain Clock Gating:
      There may be significant power saving byturning off only portions of a block, for example a TCAB used in a top level block or in another TCAB. Like coarse-grain clock gating, Synphony C Compiler automates clock gating insertion for TCABs hierarchically.

      Automatic Functional Verification:
      Synphony C Compiler provides automatic functional verification to check the sequencing of clock gating for both coarse-grained as well as fine-grained clock gating.

      Integration with downstream tools:
      Synphony C Compiler automatically generates waveforms in VCD/FSDB formats to enable power measurement in down-stream power analysis tools.

      Key Benefits
      • Significant power savings: >50% for some applications
        • Power savings are over-and-above what can be achieved with gate-level clock gating in down-stream tools
      • Fully automated and easy to use
        • Eliminates time-consuming manual effort to insert clock gating, its verification and power measurement with down-stream tools

      1. The following table shows the power savings achieved on two customer designs using Synphony C Compiler. Most of the benefits in the video design come from coarse-grained clock gating, whereas most of the benefits in the wireless design come from fine-grained clock gating. Although it is not always possible to predict which technique will deliver the best results, Synphony C Compiler makes it easy to rapidly create the designs and measure the results.

        Fine-Grained Clock gatingCoarse + Fine-Grained
        Clock gating
        Video design50%53%
        Wireless design4.73%22.4%

      2. A design for a low density parity check (LDPC) decoder for the next generation wireless handset SoC achieved 23.5% reduction in dynamic power over an identical design using a standard flow.
      3. An evaluation of the effectiveness of the approach using 8 complex applications in video, imaging and wireless domains demonstrated the following:
        • Up to 50% reduction in dynamic power for executing a single task and up to 30% savings while executing a large number of tasks
        • Average power reduction of 22% for a single task and 15% over multiple tasks

      Synphony Model Compiler
      High Level Synthesis with Synphony Model Compiler

      Figure 1: Synphony Model Compiler provides a faster, more automated path from
      high level algorithm descriptions to FPGA or ASIC, prototypes, and verification flows.

      Faster and More Efficient Model Creation
      Modeling environments are popular for algorithm design and exploration because they allow concise representations of behavior at very high levels of abstraction. These environments provide sophisticated design capture, simulation, and analysis tools for multiple domains. However, problems arise when the designer needs to translate the design intent into their RTL counterparts for use with ASIC or FPGA implementation tools. In particular, traditional methods have proven to be very time consuming and/or prone to error because of re-coding and re-verification into the RTL domain. The Synphony Model Compiler solution addresses these problems by providing an easy and automated method to synthesize high-level algorithmic representations from the Simulink/MATLAB model-based environment.

      Optimizations, Exploration, and Verification from a Single Model
      Synphony Model Compiler enables rapid exploration of architectural tradeoffs from a single model and reduces errors and risk by maintaining consistent verification across multiple architecture choices and target technologies. Given the user-specified target and architectural constraints, the HLS engine automatically optimizes at multiple levels by applying pipelining, scheduling, and binding optimizations across the entire system, including IP blocks and throughout design hierarchy. Synphony Model Compiler also includes advanced technology characterizations that utilize Synplify Premier or Design Compiler for FPGA or ASIC respectively. This provides accurate timing estimation needed to make device-specific optimizations across FPGA and ASIC targets. More importantly, it increases the reliability of verification through these design project phases, regardless whether the target is for FPGA prototyping, fast architecture exploration, or ASIC implementation.

      C-Output for Earlier Software Development and Faster System Validation
      The difficult and time consuming effort of creating models for system validation and functional verification is a major challenge in today’s system modeling and verification environments. Synphony Model Compiler addresses this challenge by combining its highly efficient modeling flow with C-Output model generation. In addition to optimized RTL, the HLS engine generates flexible, high performance fixed-point ANSI-C models that can be used in virtual platforms for early software development and a variety of other system simulation environments.

      Synphony Model Compiler brings these capabilities together for the first time in a single environment that supports complete, integrated solutions with Synopsys’ FPGA implementation, ASIC implementation, and hardware-assisted verification flows.

      Improved Reliability and Time to Market
      The benefits of Synphony Model Compiler are the ability to validate algorithm concepts much earlier in the design cycle, catch functional and system level problems much earlier, and more rapidly explore design space tradeoffs. With a more automated flow from higher levels of abstraction, Synphony Model Compiler gives system and algorithm designers much more power to realize these benefits and significantly improve the reliability and time to market of their ASIC and FPGA projects.

      Features Benefits
      Synthesizable fixed-point high level IP model library
      • Eliminates writing of fixed-point models from scratch
      • Faster verification at higher levels of abstraction
      • Offers more control over results
      High Level Synthesis Optimizations and Transformations
      • Automatic system-wide pipeline insertion scheduling and resource sharing
      • IP-aware micro architecture optimization
      • Automatic retiming and pipelining at the architecture level
      • Automatic scheduling for area optimization
      • Target-aware optimization for FPGAs and ASICs
      Integrated ASIC Flow
      • Automatic generation of RTL constraints and scripts for Design Complier
      • Advanced timing estimation using Design Compiler
      • Rapid architecture exploration of speed, area and power tradeoffs
      Integrated FPGA Flow
      • Automatic generation of RTL constraints and scripts for Synplify Pro / Synplify Premier
      • Advanced timing estimation using Synplify Pro / Synplify Premier
      • Optimized resource mapping to advanced FPGA devices such as hardware multipliers, MACS, adders, memories and shift registers
      RTL Testbench Generation
      • Automatic generation of text vectors and scripts for RTL verification in VCS
      C-model Generation for Software Development and System Validation
      • Fast model creation for C-based verification
      • Begin software development earlier using virtual prototypes

      Synfora Introduces PICO Extreme

      New technology enables the implementation of larger and complex sub-systems
      By Gabe Moretti

      EDA DesignLine

      Venice, Florida — Synfora, Inc. has announced the availability of PICO ExtremeTM, and called it a breakthrough in algorithmic synthesis technology. The PICO platform automatically creates complex hardware sub-systems (application engines) from sequential untimed C algorithms. Tools based on the PICO platform allow designers to explore programmability, performance, power, area and clock frequency. PICO Extreme enables the implementation of larger and more complex sub-systems using a recursive system composition methodology based on Synfora's innovative tightly coupled accelerator blocks (TCAB) technology.

      The technology is based on the recognition that when using C to describe hardware implementations, a C procedure is semantically equivalent to a Verilog module or a VHDL entity. Therefore both recursion and hierarchy can be used to increase the efficiency of designers and tools alike. Users are able to designate parts of their algorithm as custom building blocks.

      These application-specific building blocks are C procedures that can be designed and verified standalone and then automatically integrated and scheduled as if they were primitive computing elements. In addition, TCABs can be composed of TCABs providing recursive composition of blocks to an arbitrary depth. This composition methodology improves the ability of the compiler to find better optimization, which improves performance and reduces area. With PICO Extreme, building hardware with pre-created blocks reduces the total runtime.

      Along with the TCAB technology, PICO Extreme also delivers the following capabilities for reduced power and ease of integration into the SoC:

      • An advanced clock gating scheme that enables the designer to gate the clock of a complete processing function (loop nest) as a single entity halting any activity within the processing function (including the clock tree) and only requiring one clock gating cell.
      • The ability to extract and export mapping information that enables C-RTL equivalence checking tools to verify the equivalence between PICO-generated RTL and C. This information includes design latency/throughput, bit-accurate mapping of external C variables and stream functions to RTL block interfaces including scalar, stream and memory ports, and bit-accurate mapping of internal C variables to RTL wires, registers and memory objects.
      • An option to create OCP-IP compliant host interface to ease integration into the rest of the SoC
      Here is the comparisons between different FPGA C compilers:

      BDTI Certified Results for Synfora PICO High-Level Synthesis Tool

      An FPGA-based implementation of a complex video motion analysis algorithm (BDTI Optical Flow application) using Synfora’s PICO C synthesis tools outperformed a traditional DSP processor implementation on throughput by a factor over 40x achieving a processing rate of 204 frames per second and provided a 30X price/performance advantage over DSPs. The PICO implementation required fewer code modifications to the reference code than the DSP implementation to achieve the best performance.

      According to the BDTI’s Optical Flow application analysis, the overall development efforts for the FPGA based system and the DSP based system were comparable even though somewhat different skill sets were required. Evaluation results for the PICO High Level Synthesis platform produced results with an area efficiency comparable to a hand-coded RTL design. On the second BDTI Work Flow, the design implemented with the PICO High Level Synthesis platform required only 6.4% of FPGA resources compared to 5.9% for the hand coded design.

      To evaluate the PICO High Level Synthesis platform, BDTI used two complex DSP applications. The first is an Optical Flow video motion analysis application, which was used to compare the performance and price performance of an FPGA-based implementation using PICO C synthesis tools with an implementation on a TI TMS320 DSP using TI’s software development tool chain. The second is a wireless receiver application, which was used to compare the relative cost efficiency of an implementation obtained using the PICO C synthesis flow with a Xilinx FPGA compared to an implementation which used hand-coded RTL.

      In addition, BDTI engineers using PICO C synthesis tools to independently implement designs scored the tool on a number of usability metrics including out-of-the-box experience, ease of use, the extent of modification to the reference code, skill level required, the effort required to get to a first compiling version and the total effort required.

      BDTI is an independent analysis firm that employs a rigorous evaluation methodology to measure the quality of results (performance and price-performance of designs) and usability (productivity and ease-of-use) of DSPs, FPGAs, and high-level synthesis tools. BDTI benchmark suites are recognized world-wide by processor vendors and systems developers alike as a trusted means to understand the relative capabilities of embedded processing devices and tools.

      More info: BDTI Certified Results for the Synfora PICO High-Level Synthesis Tool

      Processor Designer

      Thanks to acquisition of CoWare, Synopsys provides Processor Designer for

      Automating the Design and Implementation of Custom Processors & Programmable Accelerators

      Synopsys Processor Designer dramatically accelerates the design of both application-specific processors and configurable accelerators through automated software development tools, RTL and instruction set simulator generation from a single, high-level specification. These application-specific processors and configurable accelerators are increasingly essential to convergent system-on-chip (SoC) functionality. Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP-specific and RISC-specific features as well as SIMD and very long instruction word (VLIW) processors.
      • Integrated design environment for unified application specific processor, programmable accelerator design and software development tool generation
      • Slashes application specific processor and programmable accelerator hardware design time by months
      • Eliminates months of engineer-effort for software tool development
      • Ensures compatibility of instruction set simulator (ISS), software development tools and RTL implementation
      • Software development environment enables application software development prior to silicon availability

      Synopsys Processor Designer is an automated, application-specific embedded processor design and optimization environment that slashes months from processor hardware design time. It also eliminates months of engineer-effort typically needed for the creation of application processor-specific software development tools. Processor Designer's high degree of automation enables design teams to focus on architecture exploration and application-specific processor development, rather than on consistency checking and verification of individual tools.

      Processor Designer dramatically accelerates the design of both custom processors and programmable accelerators, including the application-specific instruction set processors (ASIPs) that are increasingly essential to convergent system-on-chip (SoC) functionality. Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP-specific and RISC-specific features as well as SIMD and VLIW architectures.

      Processor Designer's generated software development environment enables the commencement of application software development prior to silicon availability, thus eradicating a common bottleneck in embedded system development.

      The key to Processor Designer's automation is its Language for Instruction Set Architectures, LISA 2.0. In contrast to SystemC, which has been developed for efficient specification of systems, LISA 2.0 is a processor description language that incorporates all necessary processor-specific components such as register files, pipelines, pins, memory and caches, and instructions. It enables the efficient creation of a single golden processor specification as the source for the automatic generation of the instruction set simulator (ISS) and the complete suite of software development tools, like Assembler, Linker, Archiver and C-Compiler, and synthesizable RTL code. The development tools, together with the extensive profiling capabilities of the debugger, enable rapid analysis and exploration of the application-specific processor's instruction set architecture to determine the optimal instruction set for the target application domain. Processor Designer enables the designer to optimize instruction set design, processor micro-architecture and memory sub-systems, including caches.

      Processor Designer's use of a single high-level processor specification ensures the consistency of the ISS, software development tools and RTL implementation, eliminating the verification and debug effort necessitated by multiple, independently-created models.

      Operating at a high level of abstraction, Processor Designer not only eliminates the time and cost inherent in HDL-based processor design and manual tool development, but also enables hardware and software designers to customize the instruction set to their needs.

      Synopsys buys Synfora

      In addition to acquisitions of Virage and CoWare, Vast, Synopsys acquired Synfora.

      Synopsys buys Synfora assets

      EE Times

      SAN FRANCISCO—In its second major acquisition announcement of the day, EDA and IP vendor Synopsys Inc. said Thursday (June 10) it has acquired technology, engineering resources and other assets of high-level synthesis EDA vendor Synfora Inc. The financial terms of the deal, which closed Thursday, were not disclosed.

      Earlier Thursday, Synopsys (Mountain View, Calif.) said it signed a definitive agreement to acquire IP provider Virage Logic Inc. for $315 million in cash.

      Synfora (Mountain View) provides C/C++ high-level synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synopsys said the deal would strengthen its position in system-level design and verification and enhance the company's FPGA-based prototyping solutions.

      "This acquisition adds proven C/C++ high-level synthesis technology to our system-level solutions portfolio and broadens Synopsys' comprehensive solutions for block creation and optimization," said Joachim Kunkel, senior vice president and general manager of the Solutions Group at Synopsys, in a statement.

      Synopsys did not breakdown the specifics of the acquisition or say how many Synfora employees would join the company as a result of the deal. A spokesperson for Synopsys emphasized that the deal involves Synfora's high-level synthesis tool as well as other select assets, including a "really strong" engineering team.

      Brett Cline, vice president of marketing and sales at Forte Design Systems, one of the market leaders in high-level synthesis, said Synfora has not been competitive with the rest of the high-level synthesis market for some time due to its ANSI-C based technology, which he said has some fundamental limitations and is primarily focused on prototyping as opposed to real hardware design. Ultimately this resulted in an asset sale, Cline said.

      "The market for high-level synthesis is in SystemC and has been for a number of years," Cline said. "If Synopsys does intend to go after ASIC and SoC designs we welcome the opportunity to compete."


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