DMA channels used by DM6467 ARM and DSP

Unexpected stalling and potential deadlock condition often occur when there is a resource conflict between ARM and DSP. EDMA allocations must be carefully performed. The ARM Linux kernel source, arch/arm/mach-davinci/dm646x.c, shows the DM6447 chip specific setup including EDMA. Recent discussions "Which DMA (EDMA or QDMA) channels are used by the Codec Engine and Codec Server in DM6467T DVSDK 3.10?" and "DM6467T ARM hangs after Comm_create during instantiation of DSP codec with DVSDK 3.10 GA" in e2e.ti.com reveals some potential problems in DM6467T DVSDK 3.10, especially a EDMA hardware deadlock situation that arises when the same EDMA TC is used to perform writes to BOTH DSP SDMA (L1, L2, and HDVICP RAM/Buffers through SDMA port) AND slave memories (DDR2, EMIFA, HDVICP0/1 EDMA ports, or ARM TCM).

TMS320DM6467T Digital Media System-on-Chip (DMSoC) Silicon Revision 3.0 provided an advisory for "Unexpected Stalling and Potential Deadlock Condition When DSP L2 Memory Ports Used as RAM When L2 Memory Configured as Non-cache".