DM6467 EDMA Programming

Learned from Programming EDMA without EDMA3LLD package

/* EDMA register address and definitions */

#define EDMA_CC_BASE (0x01C00000) /* DM646x. Check address for other devices. */

#define DCHMAP0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0100))

#define DMAQNUM0 *((volatile unsigned int *)(EDMA_CC_BASE + 0x0240))

#define QUEPRI *((volatile unsigned int *)(EDMA_CC_BASE + 0x0284))

#define EMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0308))

#define EMCRH *((volatile unsigned int *)(EDMA_CC_BASE + 0x030C))

#define QEMCR *((volatile unsigned int *)(EDMA_CC_BASE + 0x0314))

#define CCERRCLR *((volatile unsigned int *)(EDMA_CC_BASE + 0x031C))

#define QWMTHRA *((volatile unsigned int *)(EDMA_CC_BASE + 0x0620))

#define ESR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1010))

#define IPR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1068))

#define ICR *((volatile unsigned int *)(EDMA_CC_BASE + 0x1070))

#define PARAMENTRY0 (0x01C04000) /* DM646x. Check address for other devices. */

#define OPT *((volatile unsigned int *)(PARAMENTRY0 + 0x00))

#define SRC *((volatile unsigned int *)(PARAMENTRY0 + 0x04))

#define A_B_CNT *((volatile unsigned int *)(PARAMENTRY0 + 0x08))

#define DST *((volatile unsigned int *)(PARAMENTRY0 + 0x0C))

#define SRC_DST_BIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x10))

#define LINK_BCNTRLD *((volatile unsigned int *)(PARAMENTRY0 + 0x14))

#define SRC_DST_CIDX *((volatile unsigned int *)(PARAMENTRY0 + 0x18))

#define CCNT *((volatile unsigned int *)(PARAMENTRY0 + 0x1C))

/* Allocate srcBuff and dstBuff. Do a cache flush and cache invalidate,if required. */

#define BUFFSIZE 32

int16_t SrcBuf[BUFFSIZE]; // Src of transfer

int16_t DstBuf[BUFFSIZE]; // Dst of transfer

/* Step 1: EDMA initialization */

QUEPRI=0x10;

QWMTHRA =(16<<8u)|(16& 0xFF);

EMCR = 0xFFFFFFFF;

CCERRCLR = 0xFFFFFFFF;

/* Step 2: Programming DMA Channel (and Param set) */

DCHMAP0=0x0;

DMAQNUM0=0x0;

OPT = 0x00100000; /* only TCINTEN is set */

SRC = (unsigned int)SrcBuf;

A_B_CNT = ((1 << 16u) | (BUFFSIZE & 0xFFFFu)); /* ACNT = BUFFSIZE, BCNT = 1 */

DST = (unsigned int)DstBuf;

SRC_DST_BIDX = (BUFFSIZE << 16u) | (BUFFSIZE & 0xFFFFu); /* SRC_BIDX = BUFFSIZE, DST_BIDX = BUFFSIZE */

LINK_BCNTRLD = (1 << 16u) | 0xFFFFu; /* LINK = 0xFFFF, BCNTRLD = 1 */

SRC_DST_CIDX = 0;

CCNT = 1;

/* Step 3: Triggering the Transfer and Waiting for Transfer Completion */

ESR = 0x1;

while(((IPR) & 0x1) == 0);

/* Transfer has completed, clear the status register. */

ICR=0x01;

/* Transfer is complete. Compare the srcBuff and dstBuff *

For more information see the TMS320DM646x DMSoC Enhanced Direct Memory Access (EDMA) Controller User’s Guide http://focus.ti.com/lit/ug/sprueq5b/sprueq5b.pdf