The following paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.
Tuesday, December 30, 2008
Wednesday, December 24, 2008
What is behind?
Thursday, December 18, 2008
Bluespec presents the hardware designer an exciting new way to simplify the complexity of constructing control logic while retaining full control over the architecture and performance of the design.
Bluespec’s ESL synthesis toolset for control logic and complex datapath designs significantly accelerates hardware design & reduces verification costs delivering:
- Over a 50% reduction in time to a verified design;
- Less than 50% of the bugs compared to RTL design;
- Design exploration and feature changes can be made correctly and much more quickly
Bluespec small examples:
Thursday, December 11, 2008
Sunday, December 7, 2008
Wolfgang Hoeflich from AMI Semiconductor described how a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.
Synplicity Inc. has released Identify Pro tool allows full visibility into FPGA-based ASIC prototyping in 2007
SimGen is an EDIF/VHDL/FPGA to ASIC Conversion Utility and Simulation Generator for Tanner Tools EDA.
On Semiconductor provide services of FPGA-toASIC
Epson has a FPGA to ASIC conversion
NEC also has a conversion and demonstrated why this conversion was needed
Saturday, December 6, 2008
A tutorial for booting a fully functional operating system based on the Linux 2.4 kernel on a Xilinx University Program Virtex II-Pro based development board was presented by John H. Kelm. Furthermore, a reconfigurable hardware accelerator that can be accessed directly by applications or via a character device driver was described.
Crosstool that is a software package created by Dan Kegel that allows x86 Step 11 Linux machines to target the PowerPC405 core of the XUP board was applied.
In the MEMOCODE 2007 (the 5th), the basic design challenge was to implement a high-performance Matrix-matrix multiplication (MMM) using any HW and SW design methodology and targeting any FPGA development platform of the contestants’ choice.
In the MEMOCODE 2008, the hardware accelerated crypto sorter designs were proposed for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. The MIT team won the top honor. The code is in OPENCORE. The documentation can be downloaded from OPENCORE also.
The following link listed some the submission and the corresponding documentations: