Thursday, November 26, 2009

IP camera boasts 1080p video at 30fps

By Eric Brown

Texas Instruments (TI) announced a DaVinci-family, HD-ready Internet Protocol (IP) camera reference design. The Linux-ready DM368IPNC-MT5 is built by Appro Photoelectron, incorporates a TI DM36x-400 SoC, and can process H.264 main-profile 1080p video at 30fps while consuming only three Watts, says TI.

The DM368IPNC-MT5 is designed for cost-sensitive products requiring full HD video, such as IP cameras or IP modules for closed-circuit TV cameras, says TI. Equipped with a five megapixel Micron Aptina CMOS sensor, the DM368IPNC-MT5 IP reference design provides an Ethernet port, a RS485 serial port, a SD card, a USB interface, and Composite video output, says TI. The 2.4 x 1.8 x 3.4-inch (60 x 45 x 87mm) camera is claimed to utilize only three Watts, and includes a TI Power-over-Ethernet (PoE) "solution," called the TPS23753.

DM368 IP camera design block diagram

(Click to enlarge)

The DM368 design provides 30 percent more host processing performance than TI's previous generation IP camera reference design, offering "more headroom for differentiation and video analytics," says the company. TI appears to be comparing the DM368 design to the DM365 camera design (pictured below, right), announced in March, which was also developed in partnership with Appro.

New DM368 IP camera design (left) and earlier DM365 design (right)

The DM365 reference design is built on what TI calls a "new" DaVinci processor, the TI DM36x-400. A search for a "TMS320DM3658" DaVinci part comes up empty, but whatever the actual name of the processor, the TI DM36x-400 is likely to be a 400MHz variation of the 300Mhz TMS320DM365 SoC (system-on-chip) available with the DM365 IP camera design.

The TMS320DM365 began sampling in March, and was billed as is a higher-end version of TI's sub-$10, 720p-capable TMS320DM355, which launched in late 2007 and has been used in previous TI IP camera reference designs. Recently, TI also shipped a similar TMS320DM357SoC model that is twice as expensive as the older DM355, but which adds H.264 compression, an Ethernet MAC, and a DDR2 memory controller.

Aimed at media playback and camera-driven applications, the DM365 SoC is equipped with a 300MHz ARM926EJ-S core, plus multiple on-board peripherals. Like other DaVinci processors, it is available with a Linux-ready evaluation kit.

The SoC was touted as capable of processing 720p video at 30 frames per second (fps) or 1080p at a reduced frame rate, using the H.264 format. By comparison, the new DM36x-400 SoC and camera design boast 720p video at 60fps or 1080p at 30fps using H.264. The new design is also capable of processing 720p at 60fps using MPEG-4, or MJPEG video processed at five megapixels running at 15fps, says the company.

Like the DM365, the TI DM36x-400 offers TI's fifth-generation ISP (image signal processor), which is exploited by the new IP camera, says TI. The ISP is said to enable video stabilization, face detection, and other video quality enhancements. Other embedded functionality is said to include a web server and support for motion detection.

Linux package offers ISP tuning, encryption support

All these functions are supported by a royalty-free Linux application software package, offered with source code. The package includes an ISP Tuning Tool 1.0, a hardware-accelerated AES encryption module, and support for the Physical Security Interoperability Alliance standard (PSIA), says the company.

The software is also said to support the camera's global dynamic range enhancement (GDRE) capability. GDRE is said to enable users to "bring out details in the shadows of the video without washing out the highlights, a critical feature for video surveillance."


The DM368IPNC-MT5 IP camera reference design is available now for $995 from Appro, here, says TI. A TI page on the camera should be here.

TI will demonstrate the design at the the Global Sourcing Conference on Public Safety and Security (CPSE), on November 1-4 at the Shenzhen Convention and Exhibition Center, Futian Central District, Shenzhen, China. TI's booth may be found in Hall 1, Overseas Area A, #B218 - B223.

Thursday, November 12, 2009

United Technologies To Buy GE's Security Business for $1.82B

HARTFORD, Conn. – United Technologies Corp. (NYSE:UTX), today announced it has reached an agreement to purchase the GE Security business from GE (NYSE: GE) for $1.82 billion. The closing is pending regulatory approvals.

GE Security, part of GE Technology Infrastructure, supplies security and life safety technologies through a broad product portfolio for commercial and residential applications that include fire detection and life safety systems, intrusion alarms, and video surveillance and access control systems. Headquartered in Bradenton, Fla., the business has eight manufacturing facilities and approximately 4,700 employees in 26 countries.

"This acquisition enhances UTC Fire & Security’s status as a leading franchise in the $100 billion global fire safety and electronic security industry," UTC President and Chief Executive Officer Louis ChĂȘnevert said. "It strengthens our North America footprint, extends our capabilities and complements our existing fire and security businesses."

"The acquisition also brings additional world class product lines to the UTC portfolio, improves our aftermarket revenue potential and will deliver solid long-term value for UTC shareholders," ChĂȘnevert continued. "We expect this transaction will be earnings neutral to UTC in 2010, after restructuring and transaction costs, and anticipate that the cost synergies will make it accretive in 2011 and beyond.”

Headquartered in Connecticut, UTC Fire & Security is a business unit of United Technologies Corp., which provides high technology products and services to the building and aerospace industries worldwide. More information about UTC Fire & Security can be found at website:

Sunday, November 8, 2009

Lowest Cost, Lowest Power FPGAs - Cyclone IV

SAN JOSE, Calif.--(EON: Enhanced Online News)--Expanding on the success of the Cyclone® FPGA series and extending its transceiver leadership, Altera Corporation (NASDAQ:ALTR) today announced the new Cyclone IV FPGA family. Responding to increased low-cost bandwidth needs driven by the demand for mobile video, voice, and data access, and the hunger for high-quality 3D images, the new Cyclone IV FPGA family adds support for mainstream serial protocols while offering an optimal balance of low cost, low power and a rich supply of logic, memory and DSP capabilities.

“By rivaling the cost of ASSPs and offering unmatched flexibility, Cyclone IV FPGAs are the obvious choice for next-generation designs. The innovative features of the Cyclone IV family make it easy for designers to support multiple protocols, simplify board design and create obsolescence-proof solutions that will outlast ASSPs.”

The Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements (LEs), up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe). With low power consumption and packages as small as 11x11 mm, these devices address cost-sensitive, small form-factor applications in the wireless, wireline, broadcast, industrial and consumer markets. Cyclone IV E devices deliver an unprecedented combination of low cost and high functionality, and lower power by up to 25 percent compared to previous generation Cyclone products for power-sensitive applications such as handheld software-defined radio.

"Cyclone IV FPGAs will expand the reach of FPGAs like never before," said Vince Hu, vice president of product and corporate marketing at Altera. "By rivaling the cost of ASSPs and offering unmatched flexibility, Cyclone IV FPGAs are the obvious choice for next-generation designs. The innovative features of the Cyclone IV family make it easy for designers to support multiple protocols, simplify board design and create obsolescence-proof solutions that will outlast ASSPs."

For the Cyclone IV GX devices, Altera focused on reducing the total system cost. By integrating transceivers, Cyclone IV GX FPGAs eliminate external component costs and reduce power consumption up to 30 percent compared to previous generation Cyclone products combined with external transceiver PHYs. This power savings also reduces costs by eliminating the need for heat-dissipation hardware. Cyclone IV GX devices require only two power supplies which significantly simplifies PCB design and reduces board space and cost. With a focus on low cost, Cyclone IV GX smallest device is the industry’s smallest FPGA with transceivers.

Pricing and Availability

Production shipments of the EP4CGX15 and EP4C115E, the first Cyclone IV GX and Cyclone IV E devices respectively, will begin in the first quarter of 2010. Budgetary pricing for the smallest devices, the EP4CE6 and the EP4CGX15, will start as low as $3 and $6 respectively for 250K unit quantities in 2010. The three smallest Cyclone IV GX devices will be supported in the Quartus® II design software version 9.1 with the remaining Cyclone IV devices supported in the Quartus II design software version 9.1 service pack 1. For additional information regarding Altera's Cyclone IV FPGAs, visit

More news came from EEtimes:

Wednesday, November 4, 2009

Low cost, Low power, and High performance FPGA - Spartan-6

The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,400 to 148,000 logic cells, with half the power consumption of previous Spartan families and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power-optimized high speed serial transceiver blocks, PCI Express™ compatible Endpoint blocks, advanced system-level power management modes, autodetect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost programmable alternative to custom ASIC products with unprecedented ease-of-use. Spartan-6 FPGAs offer the best solution for highvolume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins.

Where Low Cost, Low Power Converge with High Performance

When design requirements call for low cost and low power, the new Spartan®-6 family is the answer. This silicon foundation of the Xilinx Targeted Design Platform merges industry leading process and programmable logic technology with transceiver capabilities and controllers for advanced memory support to deliver a high-performance FPGA for cost sensitive applications. Innovation in advanced power management technology and the ability to operate at a lower power 1.0V core option enable the new Spartan-6 FPGA family to achieve 65% lower power than previous Spartan families.

At the Heart of Innovation

The sixth generation in the Spartan FPGA Series enables system developers to meet demands for new features, while at the same time reducing system costs by up to half for lower-power, ”greener” products. Supporting applications such as automotive infotainment, flat-panel displays, multi-function printers, set-top boxes, home networking, and video surveillance, Spartan-6 FPGAs offer an optimal balance of low risk, low cost, low power, and high performance.

A Proven, Industry-Leading Architecture

The Spartan-6 FPGA family’s efficient, dual-register six-input LUT logic structure leverages the industry’s leading Virtex® architecture to enable cross-platform compatibility and to increase system performance. The addition of Virtex-series system-level blocks including
DSP slices, high-speed transceivers, and PCI Express® endpoint block make for greater system-level integration than ever before

The Spartan-6 family is priced at between about $3 and $54 in high volume of 10,000 units, according to Brent Pryzbus, director of product marketing, according to EETimes.

Dispersed Storage Blog

Trends in the advancement of storage virtualization: advanced data virtualization

Advanced data virtualization (Part 1)
After attending the recent SNW in Phoenix, and having some time to synthesize and digest, I’m convinced that the storage virtualization products on the market today are a good first step, but are going to have to evolve.

Over the next few weeks, I’ll offer several trends we foresee will occur to realize true storage virtualization. This week’s post will focus on the trend of advanced data virtualization.

Storage virtualization is creating efficiencies by inserting a layer of abstraction between data and storage hardware, and that same concept can be taken further to present a layer of abstraction between data and the method in which data is stored.

RAID is actually a well-known form of data virtualization because the linear sequence of bytes for data are transformed to stripe the data across the array, and include the necessary parity bits. RAID’s data virtualization technique was designed over 20 years ago to improve data reliability and I/O performance, and it is now in the process of failing as we transition from structured data to large quantities of unstructured data.

Dispersal, as we’ve discussed in numerous posts on this blog, is a natural successor for RAID for data virtualization because it can be configured with M of N fault tolerance, which can provide much higher levels of data reliability than RAID. Dispersal essentially packetizes the data (N packets), and only requires a subset (M packets) to bit perfectly recreate the data.

One major change for data virtualization that will occur as Dispersal replaces RAID is that there will no longer be a tight coupling between hardware and the storage of the data packets. This will eliminate the concept of having copies of data on hardware.

Today’s RAID systems stripe data and parity bits across disks within an array within an appliance. When asked “Where is my data?” the answer is typically “On this piece of hardware.” This gives people peace of mind in terms of sensing something that is intangible (since the data is actually virtualized) is actually tangible because it is contained within a physical device.

The shift for people will be from asking “Where is my data?” since it will be virtualized across multiple devices in multiple locations to “Is my data protected?” because the root of the first question is the second. Once people can get comfortable with actually giving up control of actually knowing exactly where their data resides, they will realize the benefits of data virtualization. A future post in this series will discuss how management systems will need to evolve to address Data Protection concerns.

The largest benefit to storing data packets across multiple hardware nodes is increased fault tolerance. RAID basically is structured to provide disk drive fault tolerance – as disk fails, and the other disks can reconstruct the data. Dispersal provides not only disk drive level fault tolerance, but also device drive fault tolerance, and even location fault tolerance. When an entire device fails, the data can be reconstructed from virtualized data packets on other devices, whether centrally located or across multiple sites.

We’ll discuss location fault tolerance in more detail in the next post.


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