Xilinx FPGA "Writing Efficient Testbenches"

This Xilinx FPGA application note

http://www.xilinx.com/support/documentation/application_notes/xapp199.pdf

is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience.

Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design.

All design files for this application note are available on the FTP site at:

https://secure.xilinx.com/webreg/clickthrough.do?cid=134003&license=RefDesLicense

For Test Bench Waveform Editor View, please see

http://www.xilinx.com/itp/xilinx10/isehelp/ism_r_tb_waveform_editor_view.htm

For more information about creating an HDL test bench, go to the Xilinx

Synthesis and Simulation Design Guide