This Xilinx FPGA application note
is written for logic designers who are new to HDL verification flows, and who do not have extensive testbench-writing experience.
Testbenches are the primary means of verifying HDL designs. This application note provides guidelines for laying out and constructing efficient testbenches. It also provides an algorithm to develop a self-checking testbench for any design.
All design files for this application note are available on the FTP site at:
For Test Bench Waveform Editor View, please see
For more information about creating an HDL test bench, go to the Xilinx