Verilog Simulation using Modelsim and ISE

1. If you have not compiled the Xilinx Simulation Libraries, please see (Xilinx Answer 15338) for information on how to compile the libraries.

2. Compile the "glbl.v" module, the source files, and the testbench. For example:
vlog $env(XILINX)/verilog/src/glbl.v .v .v

For more information about the "glbl.v" module, please see (Xilinx Answer 6537).

3. Load the design in ModelSim and use the -L switch to point to the libraries being used in the design. The "glbl" needs to be loaded as well.
vsim -t ps -L unisims_ver -L xilinxcorelib_ver work. work.glbl

NOTE: The "glbl.v" automatically pulses Global Set/Reset (GSR) for the first 100 ns of the simulation. See (Xilinx Answer 6537) for more information.

More see

http://www.xilinx.com/support/answers/1078.htm

http://www.xilinx.com/support/answers/1923.htm

http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/xcell/xl33/xl33_38.pdf

The following links are purely for ModelSim simulation and tutorials for Verilog:

http://web.mit.edu/6.111/www/s2005/guides/ModelSim_tutorial.pdf

http://www.stanford.edu/class/ee108b/labs/Modelsim_short_tutorial.pdf

ftp://ftp.altera.com/up/pub/Altera_Material/9.1/Tutorials/Verilog/ModelSim_GUI_Introduction.pdf

http://www.actel.com/documents/vlogsim_ug.pdf

http://pages.cs.wisc.edu/~karu/courses/cs552/spring2011/wiki/index.php/Main/SimulatingVerilogTutorial