2. Compile the "glbl.v" module, the source files, and the testbench. For example:
For more information about the "glbl.v" module, please see (Xilinx Answer 6537).
3. Load the design in ModelSim and use the -L switch to point to the libraries being used in the design. The "glbl" needs to be loaded as well.
vsim -t ps -L unisims_ver -L xilinxcorelib_ver work.
NOTE: The "glbl.v" automatically pulses Global Set/Reset (GSR) for the first 100 ns of the simulation. See (Xilinx Answer 6537) for more information.
The following links are purely for ModelSim simulation and tutorials for Verilog: