Synopsys Verilog Compiler Simulator (VCS), Xilinx ISE and Novas Tools

VCS is a tool from Synopsys specifically designed to simulate and debug design. To compile the Verilog source code, run

vcs "-o" "simv" "+v2k" "-sverilog" "+vcsd" "+memcbk" "+vcs+initmem+x" "+libext+.v" "-y" "." "-P" "/novas/share/PLI/vcsd_mhpi_latest/LINUX/novas.tab" "/novas/share/PLI/vcsd_mhpi_latest/LINUX/pli.a" +incdir+../src -top test_top -f run.f

For post synthesis simulation, when Xilinx ISE is installed,

vcs -o simv +v2k -sverilog -y $XILINX/verilog/src/unisims +incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v -f vmtest.f -top:test_top

If compiling is successful, by default the output of compilation would be a executable binary file is named simv. Run simv for simulation.