The areas that grew during 2000-2009 are DFM- 33 percent CAGR, ESL — 12 percent, Formal verification – 11 percent, IC/ASIC analysis – 9 percent, respectively.
System level issues have also become a bigger part of chip and board design. Among Dr. Rhines outlined eight critical and emerging system design challenges, system level optimization has biggest impact on performance and power. ESL provides the next design abstraction. It provides fast hardware/software validation platform, as well as more opportunity for architectural exploration. The architectures are optimized before committing to RTL.