Using Synplify, ISE/XPS, ActiveHDL and ModelSim

Synplify products (versions 6.2 and higher) have been integrated with Xilinx ISE (Integrated Synthesis Environment)

http://www.synplicity.com/syndicated/pdf/XilinxISE_v1_3.pdf

http://www.commlogicdesign.com/pubs/synplicity_edk_appnote_short.pdf

and XPS (Xilinx Platform Studio)

http://ww.synplicity.com/literature/syndicated/pdf/v4_i2/platform_studio_v4_i2.pdf 


The following lab guide is for Using Synplify Pro, ISE and ModelSim:

http://ens.ewi.tudelft.nl/Education/courses/et4351/manual.pdf

A Xilinx ModelSim Simulation Tutorial from Upenn

http://www.cis.upenn.edu/~milom/cse372-Spring06/simulation/

An application note presents the design flow for systems created with Xilinx EDK 7.1i with Active-HDL 6.3 SP1 and Xilinx ISE 7.1i:

http://support.aldec.com/SupportArchive/PDFs/000381_SimulatingXilinxEDK7.1ProjectswithActiveHDL6.3.