Thursday, December 18, 2008


Bluespec presents the hardware designer an exciting new way to simplify the complexity of constructing control logic while retaining full control over the architecture and performance of the design.

Bluespec’s ESL synthesis toolset for control logic and complex datapath designs significantly accelerates hardware design & reduces verification costs delivering:

  1. Over a 50% reduction in time to a verified design;
  2. Less than 50% of the bugs compared to RTL design;
  3. Design exploration and feature changes can be made correctly and much more quickly

Bluespec learning documentations:

Import C to Bluespec:

Some blogs about Bluespec:

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