The ISE™ design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click a box in the following figure.
Create an ISE project as follows:
- Create a project.
- Create files and add them to your project, including a user constraints (UCF) file.
- Add any existing files to your project.
- Assign constraints such as timing constraints, pin assignments, and area constraints.
You can verify the functionality of your design at different points in the design flow as follows:
- Before synthesis, run behavioral simulation (also known as RTL simulation).
- After Translate, run functional simulation (also known as gate-level simulation), using the SIMPRIM library.
Implement your design as follows:
- Place and Route
- Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:
- Synthesize and implement your design again until design requirements are met.
You can verify the timing of your design at different points in the design flow as follows:
- Run static timing analysis at the following points in the design flow:
- Run timing simulation at the following points in the design flow:
Xilinx Device Programming
Program your Xilinx device as follows:
- Create a programming file (BIT) to program your FPGA.
- Generate a PROM, ACE, or JTAG file for debugging or to download to your device.
- Use iMPACT to program the device with a programming cable.
Go to the ISE Quick Start Tutorial to get an idea of the additional capabilities of ISE.