Useful Bluespec Examples

To store vectors or read in vectors in the testbench, a RegFile can be applied to initialize its contents at start of simulation.

// Copyright 2008 hdfpga.blogspot.com  All rights reserved.

package Tb;

import FIFO ::*;

import Vector ::*;

import FIFOF ::*;

import RegFile::*;

(* synthesize *)

module mkTb (Empty);

  RegFile#(Bit#(9), Bit#(8)) rFile <- mkRegFileLoad("test.dat", 0, 15);

  Reg#(Bit#(9)) cnt <- mkReg(0);

  rule readAndDisp(cnt <>

       $display("#%03d: 0x%02x", cnt, rFile.sub(cnt));

       cnt <= cnt + 1;

  endrule

  rule finished(cnt == 15);

       $display("Finished");

       $finish(0);

  endrule

endmodule: mkTb

endpackage: Tb

Moreover, to feed data from RegFile to an application:

// Copyright 2008 hdfpga.blogspot.com  All rights reserved.

package mkTb;

import FIFO ::*;

import Vector ::*;

import FIFOF ::*;

import RegFile::*;

import Connectable::*;

import GetPut::*;

interface IInputGen;

    interface Get#(Vector#(4, Bit#(8))) ioout;

endinterface

interface ITestApp;

    interface Put#( Vector#( 4, Bit#(8)) ) ioin;

    interface Get#( Vector#(16, Bit#(8)) ) ioout;

endinterface

(* synthesize *)

module mkInputGen( IInputGen );

    RegFile#(Bit#(9), Vector#(4, Bit#(8))) rfile <- mkRegFileLoad("test.hex", 0, 4);

   

    FIFO#(Vector#(4, Bit#(8)))   outfifo <- mkFIFO;

    Reg#(Bit#(9))    index   <- mkReg(0);

    rule output_byte (index <>

       //$display( "inputbyte %x", rfile.sub(index) );

       outfifo.enq(rfile.sub(index));

       index <= index+1;

    endrule

    rule end_of_file (index == 4);

       $finish(0);

      //outfifo.enq(EndOfFile);

    endrule

   

    interface Get ioout = fifoToGet(outfifo);

   

endmodule

(* synthesize *)

module mkTestApp( ITestApp );

    RWire#(Vector#(16, Bit#(8))) pix_out    <- mkRWire;

    RWire#(Vector#( 4, Bit#(8))) pix_in     <- mkRWire;

    Reg#(Bit#(9)) cnt <- mkReg(0);

    Reg#(Bit#(4)) step <- mkReg(0);

    rule process_mode( isValid(pix_in.wget()));

     Vector#(4, Bit#(8)) pix = fromMaybe( ?, pix_in.wget() );

 $display("#%03d: 0x%02x", k, pix[k]);

    endrule

    interface Put ioin;

       method Action put( Vector#(4, Bit#(8)) pix ) if (step <= 3);

     //$display ("%d 0x%02x", cnt, pix[cnt]);

            pix_in.wset(pix);

         endmethod

    endinterface

    interface Get ioout;

         method ActionValue#(Vector#(16, Bit#(8))) get() if (isValid(pix_out.wget));

              return fromMaybe(?, pix_out.wget());

         endmethod

    endinterface

endmodule

(* synthesize *)

module mkTb (Empty);

    IInputGen     inputgen    <- mkInputGen();

    ITestApp     TestApp    <- mkTestApp();

    Reg#(Bit#(8)) x <- mkReg(0);

    Reg#(Bit#(9)) cnt <- mkReg(0);

    mkConnection( inputgen.ioout, TestApp.ioin );

    rule connect;

        ///Vector#(4, Bit#(8)) pix = newVector;

        ///let x <- inputgen.ioout.get();

        //$display ("IO out %0d", x);

        //$display ("IO out 0x%02x", x);

        ///pix = x;

        ///TestApp.ioin.put(pix);

        cnt <= cnt + 1;

    endrule

  rule finished(cnt == 4);

     $display("Finished");

      $finish(0);

   endrule  

endmodule: mkTb

endpackage: mkTb