Wednesday, December 24, 2008

SAD implementation in FPGA hardware

In this paper, a new unit intended to augment a general-purpose core that is able to perform a  SAD operation was proposed. This SAD implementation can easily be extended to perform the complete SAD operation

http://citeseer.ist.psu.edu/old/487250.html

other related papers and similar documents are also listed.




1 comment:

Nadav said...

Hi,

I don't know if you know about this but C To Verilog is a website which compiles regular C code into Verilog. There is a free on-line service on the webpage. Maybe you can review it and write a post about it.

Nadav

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