Wednesday, March 30, 2011

Post-Synthesis Simulation Using Synplify, NC-verilog and ISE

A FPGA synthesis tool such as Synplify optimizes the design code and converts it from RTL to a post-synthesis netlist. A netlist can be

File Type



Netlist for Place & Route tools


Synthesized netlist for simulation


Synthesized netlist for simulation


Constraints for P&R tools

For Xilinx FPGA, we may use NC-Verilog to do a post-synthesis simulation with the ISE libraries including unisims or simprim and glpl.v. For example, a script may like

ncverilog -sv -y ${XILINX}/verilog /unisims +incdir+${XILINX}/verilog/src +libext+.v ${XILINX}/verilog/src/glbl.v test.vm -f vm.f +nctop:test -w -timescale 1ns/1ns

The vm.f includes other simulation Verilog files. -sv is for system Verilog. test is the top module of Synplify synthesis.

The following links also provide good information using NC-Verilog tools for post-synthesis simulation:

The following link shows a Conformal FPGA and Synplify Pro Flow

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