NC-Verilog Simulator and ISE

In Xilinx website, instructions are provided for simulation using NC-Verilog Simulator and ISE:

http://www.xilinx.com/support/answers/5474.htm

Two methods are available:

• Using library source files with compile-time options (similar to Verilog-XL)
• Using shared pre-compiled libraries

Please see (Xilinx Answer 2554) for information on compiling the simulation libraries for NC-Verilog

1. Using library source files with compile-time options (similar to Verilog-XL):

Depending on the makeup of the design (Xilinx instantiated primitives, CORE Generator components, etc.), for RTL simulation, specify the following at the command-line:

ncverilog -y $Xilinx/verilog/src/unisims -y $Xilinx/verilog/src/XilinxCoreLib \
+incdir+$Xilinx/verilog/src +libext+.v $Xilinx/verilog/src/glbl.v \
.v .v

The $Xilinx can be "\Xilinx\13.1\ISE_DS\ISE\" for ISE 13.1.

The "$Xilinx/verilog/src/unisims" area contains the Unified Library components for RTL simulation. The "$Xilinx/verilog/src/simprims" area contains generic simulation primitives.

For timing simulation/post-map simulation or post-translate simulation, the SimPrim-based libraries are used. Specify the following at the command-line:

ncverilog -y $Xilinx/verilog/src/simprims $Xilinx/verilog/src/glbl.v \
+libext+.v .v .v

2. Using shared pre-compiled libraries:

Simulation libraries must be compiled to before NC-Verilog is used. Please see (Xilinx Answer 2554) for instructions on compiling the Xilinx Verilog libraries.

Depending on the makeup of the design (Xilinx instantiated primitives, COREGen, etc.), for RTL simulation, edit the "hdl.var" and "cds.lib" to specify the library mapping:

# cds.lib
DEFINE unisims_ver /unisims_ver
DEFINE simprims_ver /simprims_ver
DEFINE xilinxcorelib_ver /xilinxcorelib_ver
DEFINE worklib worklib

# hdl.var
DEFINE VIEW_MAP ($VIEW_MAP, .v => v)
DEFINE LIB_MAP ($LIB_MAP, /unisims_ver => unisims_ver)
DEFINE LIB_MAP ($LIB_MAP, /simprims_ver => simprims_ver)
DEFINE LIB_MAP ($LIB_MAP, /simprims_ver => xilinxcorelib_ver)
DEFINE LIB_MAP ($LIB_MAP, + => worklib)

After setting up the libraries, compile and simulate the design:

ncvlog -messages -update $XILINX/verilog/src/glbl.v .v .v
ncelab -messages testfixture_name glbl
ncsim -messages testfixture_name

The -update option of NCVLog enables incremental compilation.

For timing simulation or post-NGDBUILD, the SimPrim-based libraries are used. Specify the following at a command line:

ncvlog -messages -update $XILINX/verilog/src/glbl.v .v time_sim.v
ncelab -messages -autosdf testfixture_name glbl
ncsim -messages testfixture_name

Please see (Xilinx Answer 947) for information on back-annotating the SDF file for timing simulation.