Sunday, March 27, 2011

NC-Verilog Simulator Tutorial

Cadence NC-Verilog Simulator is a very good FPGA simulator. The other two famous ones are Synopsys' VCS and Mentor Graphics' Modelsim. Modelsim is implemented based on interpretters, VCS and NC-Verilog are implemented based on Compilers. VCS and NC-Verilog are much faster than Modelsim.

NC-Verilog Simulator provides command line tools and GUI tool.

1. Command line tools tools

  • ncvlog: Compiles Verilog files
  • ncelab: Elaborates the design and generates a simulation snapshot
  • ncsim: Simulates the snapshot
  • ncverilog or irun: Single-step invocation

2. GUI tool

  • nclaunch

4. Single-Step Invocation With ncverilog or irun

Run the NC Verilog simulator with this command:

% ncverilog -f verilog.args

We can also include ncvlog, ncelab, and ncsim options on the ncverilog command line in the form of plus options. There are also some plus options that are specific to the ncverilog command. Running the simulator with the ncverilog command automatically creates everything you need to run the simulator, including all directories, libraries, a cds.lib file, and an hdl.var file. The simulator then translates all applicable Verilog-XL options into options for the NC Verilog simulator and then invokes the parser and compiler (ncvlog), the elaborator (ncelab), and the simulator (ncsim) sequentially to simulate the design.

The following links also give good information:

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