NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company is calling “variable symmetric multiprocessing” (vSMP) and it’s purpose is to provide extremely low-power operation during periods when the end product in an active standby mode—when it’s performing background tasks such as email and social media synchronization or running active widgets. As the NVIDIA White Paper states “Users generally do not care how fast the background tasks are processed, only that they happen and do not consume much battery life.”

Variable SMP technology has several architectural advantages compared to other solutions, such as asynchronous clocking.

Cache Coherency: Since vSMP technology does not allow both the Companion core and the main cores to be enabled at the same time, there are no penalties involved in synchronizing caches between cores running at different frequencies. The Companion and main cores share the same L2 cache, and the cache is programmed to return data in the same number of nanoseconds for both Companion and main cores (essentially it takes more “main core cycles” versus fewer “Companion core cycles” because the main cores run at higher frequency).
OS Efficiency: The Android OS assumes that all available CPU cores are identical with similar performance capability and schedules workloads to these cores accordingly. When multiple CPU cores are each run at different asynchronous frequencies, it results in the cores having differing performance capabilities. This could lead to OS scheduling inefficiencies. In contrast, vSMP technology always maintains all active cores at a similar synchronous operating frequency for optimized OS scheduling. Even when vSMP switches from the Companion core to one or more of the main CPU cores, the CPU management logic ensures a seamless transition that is not perceptible to end users and does not result in any OS scheduling penalties.
Power Optimized: Each core in an asynchronous clocking based CPU architecture is typically on a different power plane (aka voltage rail or voltage plane) to adjust the voltage of each core based on operating frequency. This could result in increased signal and powerline noise across the voltage planes and negatively impact performance. Since each voltage plane may require its own set of voltage regulators, these architectures may not be easily scalable as the number of CPU cores is increased. The additional voltage regulators increase BOM (Bill of Materials) cost and power consumption. If the same voltage rail is used for all cores, then each core will run at the voltage required by the fastest core, thus losing the advantage of the “voltage squared” effect for power reduction.

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