Saturday, September 10, 2011

H.265 Motion Estimation on FPGA

MIT students Mehul Tikekar and Mahmut E. Sinangil, mentored by Alfred Man Cheuk Ng., have developed H.265 Motion Estimation that can sustain at least 30 frames per second (fps) for 1,280 x 720-frame resolution. The project produced a design that sustains 10 fps at 50 MHz on FPGA and 40 fps at 200 MHz when synthesized with a 65-nm cell library. Motion estimation is an essential component of any digital video encoding scheme. H.265, the next-generation standard in development to follow H.264, allows variable-size coding units to increase coding efficiency. They took the BSV test lab representations and synthesized them into corresponding Verilog RTL representations. The Verilog is then synthesized into an equivalent gate-level representation that is loaded into the FPGA development board.

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