AutoESL

http://www.autoesl.com/

BDTI report:

http://autoesl.com/images/stories/BDTI/bdti_autopilot_final.pdf

BDT’s conclusion is that they “were impressed with the quality of results that AutoPilot was able to produce given that this has been a historic weakness for HLS tools in general.” The only real negative is that the tool chain is more expensive (since AutoESL doesn’t come bundled with your FPGA or your DSP).

EDA review:

http://blogs.cancom.com/elogic_920000692/2010/04/30/is-it-time-to-start-using-high-level-synthesis/

AutoESL provides a powerful high level synthesis solution that enables:

• Synthesis of complex algorithms in C, C++ or SystemC into ASICs or FPGAs
• Software architects to accelerate software algorithms by implementing them in silicon
• System architects to take software models into silicon without manually writing RTL
• Hardware architects to explore and implement the right architecture in silicon

AutoPilot™ is the industry's only high level synthesis solution that:

• Provides broadest multi-language support for C, C++ and SystemC
• Delivers QoR equal to or better than hand-coded RTL
• Optimally targets both ASICs and FPGAs
• Is suited for multiple application domains such as video, wireless, networking, accelerated computing and DSP

http://www.xilinx.com/products/design_tools/logic_design/advanced/esl/autoesl.htm#tech

Overview of the Technology

• Platform-based communication-centric synthesis
• Unified coverage of C,C++, and SystemC languages
• Advanced code transformations
• Highly scalable ESL optimization
• Direct synthesis of single and double precision floating point operations
• Black-box Xilinx FPGA core support
• Automatic RTL test bench generation
• Industry standard Eclipse user interface
• Generates synthesizable VHDL, Verilog HDL, and SystemC code