CatapultC, Forte's Cynthesizer, and Cadence's C-to-Silicon tools:
Synfora Introduces PICO ExtremeNew technology enables the implementation of larger and complex sub-systems
By Gabe Moretti
(02/11/2008 10:30 AM EST)
Venice, Florida — Synfora, Inc. has announced the availability of PICO ExtremeTM, and called it a breakthrough in algorithmic synthesis technology. The PICO platform automatically creates complex hardware sub-systems (application engines) from sequential untimed C algorithms. Tools based on the PICO platform allow designers to explore programmability, performance, power, area and clock frequency. PICO Extreme enables the implementation of larger and more complex sub-systems using a recursive system composition methodology based on Synfora's innovative tightly coupled accelerator blocks (TCAB) technology.
The technology is based on the recognition that when using C to describe hardware implementations, a C procedure is semantically equivalent to a Verilog module or a VHDL entity. Therefore both recursion and hierarchy can be used to increase the efficiency of designers and tools alike. Users are able to designate parts of their algorithm as custom building blocks.
These application-specific building blocks are C procedures that can be designed and verified standalone and then automatically integrated and scheduled as if they were primitive computing elements. In addition, TCABs can be composed of TCABs providing recursive composition of blocks to an arbitrary depth. This composition methodology improves the ability of the compiler to find better optimization, which improves performance and reduces area. With PICO Extreme, building hardware with pre-created blocks reduces the total runtime.
Along with the TCAB technology, PICO Extreme also delivers the following capabilities for reduced power and ease of integration into the SoC:
- An advanced clock gating scheme that enables the designer to gate the clock of a complete processing function (loop nest) as a single entity halting any activity within the processing function (including the clock tree) and only requiring one clock gating cell.
- The ability to extract and export mapping information that enables C-RTL equivalence checking tools to verify the equivalence between PICO-generated RTL and C. This information includes design latency/throughput, bit-accurate mapping of external C variables and stream functions to RTL block interfaces including scalar, stream and memory ports, and bit-accurate mapping of internal C variables to RTL wires, registers and memory objects.
- An option to create OCP-IP compliant host interface to ease integration into the rest of the SoC
BDTI Certified Results for Synfora PICO High-Level Synthesis Tool
An FPGA-based implementation of a complex video motion analysis algorithm (BDTI Optical Flow application) using Synfora’s PICO C synthesis tools outperformed a traditional DSP processor implementation on throughput by a factor over 40x achieving a processing rate of 204 frames per second and provided a 30X price/performance advantage over DSPs. The PICO implementation required fewer code modifications to the reference code than the DSP implementation to achieve the best performance.
According to the BDTI’s Optical Flow application analysis, the overall development efforts for the FPGA based system and the DSP based system were comparable even though somewhat different skill sets were required. Evaluation results for the PICO High Level Synthesis platform produced results with an area efficiency comparable to a hand-coded RTL design. On the second BDTI Work Flow, the design implemented with the PICO High Level Synthesis platform required only 6.4% of FPGA resources compared to 5.9% for the hand coded design.
To evaluate the PICO High Level Synthesis platform, BDTI used two complex DSP applications. The first is an Optical Flow video motion analysis application, which was used to compare the performance and price performance of an FPGA-based implementation using PICO C synthesis tools with an implementation on a TI TMS320 DSP using TI’s software development tool chain. The second is a wireless receiver application, which was used to compare the relative cost efficiency of an implementation obtained using the PICO C synthesis flow with a Xilinx FPGA compared to an implementation which used hand-coded RTL.
In addition, BDTI engineers using PICO C synthesis tools to independently implement designs scored the tool on a number of usability metrics including out-of-the-box experience, ease of use, the extent of modification to the reference code, skill level required, the effort required to get to a first compiling version and the total effort required.
BDTI is an independent analysis firm that employs a rigorous evaluation methodology to measure the quality of results (performance and price-performance of designs) and usability (productivity and ease-of-use) of DSPs, FPGAs, and high-level synthesis tools. BDTI benchmark suites are recognized world-wide by processor vendors and systems developers alike as a trusted means to understand the relative capabilities of embedded processing devices and tools.