Thursday, February 17, 2011

Genesys Logic External PHY

The GL9714 is a 4-lane PCI Express PHY Layer Controller, which is compliant with PCI Express Base Specification rev. 1.0a and Intel’s PHY Interface for the PCI Express Architecture rev. 1.0. It integrates a quad SerDes and the Physical Coding Sub-layer (PCS) which performs 8b/10b encoding and decoding, elastic buffer and receiver detection, data serialization and deserialization for each lane. The quad SerDes in the GL9714 supports an effective serial interface speed (2.5 Gb/s) of data bandwidth for each lane, intended for use in ultrahigh-speed bi-directional data transmission system.

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