H.264 CoDec SoCs: the differentiation begins
Not that long ago SoC designers were looking at the emerging H.264 video CoDec specification and asking how the heck they were supposed to do that. They apparently figured out some answers, because the initial trickle of software and FPGA CoDecs is turning into a stream of single-chip devices. And now, with a new generation of chips taping out, we are starting to see some patterns that could amount to differentiation in the market.
To begin with, there is the question of bit rates, resolution and power. It appears that there may be viable points in the market for both very-low-power chips that work at moderate resolution—say, D1—and for higher-power devices that can handle full 1080p resolution. Another key parameter here that is rarely discussed is frame rate. While many CoDec vendors are quietly targeting 30 or 40 frames per second at 1080p, display vendors are escalating the frame rate in an attempt to suppress visible time-domain artifacts. There is a difference of opinion developing here.
There is also the matter of the handset video market. There’s not yet a lot of announced activity for mobile devices such as smart phones, but then there is not yet a lot of agreement about the appropriate resolution and color depth for hand-held video viewing, either. Early entrants in the handset market risk underestimating the image quality needs of the system OEM in their eagerness to meet his power requirements.
Another, and less obvious, area of differentiation is the time domain. An architecture announcement—one of those “we haven’t taped out yet but we want to get our name in play” releases—by W&W Communications is a case in point. The company’s Taos architecture appears to be geared not for highest compression ratios, but for three apparently unrelated attributes: very low latency, rapid error recovery and a high degree of video stream multiplexing.
So why these things? The main answer appears to be video surveillance. Low latency is necessary if you want to be able to respond to the appearance of an object of interest while it is still there—for example, if you’d like to move a camera to track an intruder who suddenly appears at the edge of the field, or if you’d like to zoom in on a face to give your lame face-recognition algorithm half a chance of not mistaking the vice president of manufacturing for Richard Nixon again.
Similarly, security monitor systems typically multiplex a large number of cameras through as small a pipe as possible for cost reasons. So the ability to use one relatively expensive (about $50) CoDec chip for a number of cameras is a good idea. And error recovery is an important issue in latency as well. If an error in the encoded bit stream causes the loss of four subsequent frames, the fact that you have a wonderful compression ratio may not be all that relevant.
The surest way to achieve these attributes is through elimination of B-frames and use of P-frames only as necessary to reach the target bit rate. This also simplifies the encoding a fair bit, reducing the amount of motion estimation that is necessary, the number of frames that must be stored internally, and the number of modes that must be explored. And in surveillance applications, bit rate is usually not as critical a parameter as it might be in, say, video broadcast.
Just what impact these choices have had on the Taos internal architecture is hard to say, since W&W’s architecture announcement didn’t actually say a lot about the architecture. But given that the company has the design running in FPGAs at 110 MHz doing 1080p 30 frames/second encode, if I understood correctly, the actual CoDec pipeline must be something of a wonder of simplicity. It appears that there are some rather elegant ideas in there, if we ever get to see them.
As more information emerges about this and other new-generation CoDec designs it will be very interesting to compare the algorithmic and architectural decisions of the W&W design team with, for instance, those of the Mobilygen team. It should make an excellent study in how details in the choice of market—and hence details in the design requirements—get reflected at the macro level in the chip architecture and implementation.