FPGA Design Tools

Xilinx ISE 10.1

• Logic design - Delivering optimal timing closure for higher performance, lower power designs
• Embedded systems – Design wizards accelerate processing development and time-to-market
• DSP design - Flows and IP tailored for algorithm, system, and hardware developers

Embedded Design Tools

• Platform Studio and the EDK 
  An integrated development environment of embedded processing tools, MicroBlaze soft processor core, IP, SW libraries, and design generators
• Xilinx Embeddable FPGACore

Learn more about all Embedded Design products and technologies

DSP Design Tools

• System Generator for DSP 
  Enables development of high-performance DSP systems using products from The MathWorks, Inc.
• AccelDSP™ Synthesis Tool 
  Option to System Generator for DSP enabling a top-down MATLAB language-based DSP design methodology

Learn more about the DSP Design products and technologies

Logic Design Tools

• ISE Foundation™ Software 
  The industry's most complete programmable logic design solution
• ISE WebPACK™ Software 
  A FREE solution for your Xilinx CPLD or medium-density FPGA design.
• ChipScope™ Pro Tool 
  Leading-edge, real-time debug and verification tools for Xilinx FPGAs.
• ChipScope Pro Serial IO Toolkit 
  An optional add-on allowing quick and easy set up for serial IO channels.
• PlanAhead™ Design Analysis Tool 
  An intuitive environment for faster, more efficient solution for performance goals.
• ISE Simulator 
  A complete, full-featured HDL simulator integrated with ISE Foundation.
• ModelSim Xilinx Edition-III (MXE-III) 
  A low cost version of the industry's most popular simulation environment.
• ISE Classics 
  A FREE collection of previously released ISE software tools.

Altera Quartus II 

The Quartus II software now features unique advantages in design flow methodology, system design, timing-closure methodology, in-system verification technology, and third-party EDA support. Highlights of Quartus II software FPGA design flow features are provided below. Figure 1 shows a high-level example of some of the Quartus II software FPGA design flow options. Some steps can be performed in a different order than shown in Figure 1.

Figure 1. FPGA Design Flow

Mento Graphics Modelsim

As advanced FPGAs have grown to ASIC proportions in terms of size and complexity, their design and verification have become correspondingly more difficult. This has driven the need for greater expertise in the design and verification of FPGAs. ModelSim provides industry leading standards-based simulation and verification platform for the FPGA market. We help you address and overcome challenges that you face everyday with the following solutions:

HDL Simulation

ModelSim offers a native environment with support for multiple languages including VHDL, Verilog, SystemC, and SystemVerilog. The integrated verification and debug environment finds more bugs faster and enhances performance with the mixed-HDL flow.

http://www.model.com/solutions/fpga_design.asp

Mento Graphics Synthesis

Precision Synthesis is the most advanced synthesis tool for all FPGA applications including complex designs and ASIC prototyping. Precision Synthesis forms the centerpiece of Mentor Graphics FPGA flow — the industry's most comprehensive vendor-independent solution for FPGA design. Precision Synthesis provides high quality of results, interactive design flows and award winning analysis. These capabilities reduce design iterations, and enable faster, more predictable completion of designs.

With over 3000 seats worldwide, Mentor Graphics synthesis solutions support all the major FPGA vendors: Actel, Altera, Atmel, Lattice, QuickLogic, and Xilinx.

Mento Graphics Catapult C Synthesis

Catapult C Synthesis is for ASIC and FPGA hardware designers of portable wireless, video, and image processing equipment who need to deliver optimal implementations with aggressive time-to-market requirements. Catapult C Synthesis is a high-level synthesis tool that uses industry-standard ANSI C++ to generate correct-by-construction, high-quality RTL 10-100x faster than other methods. Unlike traditional RTL design methodologies, Catapult C Synthesis enables the designer to pick the best architecture for given performance/area/power requirement and avoids the design errors introduced from hand coding the RTL description.