Designing FPGAs and ASICs

The following presentation gives a good overview of design:

 http://vlsi1.engr.utk.edu/ece/bouldin_courses/551/overview-slides-color.pdf

Using Synplify, ISE/XPS, ActiveHDL and ModelSim

Synplify products (versions 6.2 and higher) have been integrated with Xilinx ISE (Integrated Synthesis Environment)

http://www.synplicity.com/syndicated/pdf/XilinxISE_v1_3.pdf

http://www.commlogicdesign.com/pubs/synplicity_edk_appnote_short.pdf

and XPS (Xilinx Platform Studio)

http://ww.synplicity.com/literature/syndicated/pdf/v4_i2/platform_studio_v4_i2.pdf 


The following lab guide is for Using Synplify Pro, ISE and ModelSim:

http://ens.ewi.tudelft.nl/Education/courses/et4351/manual.pdf

A Xilinx ModelSim Simulation Tutorial from Upenn

http://www.cis.upenn.edu/~milom/cse372-Spring06/simulation/

An application note presents the design flow for systems created with Xilinx EDK 7.1i with Active-HDL 6.3 SP1 and Xilinx ISE 7.1i:

http://support.aldec.com/SupportArchive/PDFs/000381_SimulatingXilinxEDK7.1ProjectswithActiveHDL6.3.

XUPV2P and 1G DIMM Memory Modules

It seems the board can support up to 2G DIMM Memory Modules. The following link is a datasheet of 1G DIMM Memory Modules

http://www.supertalent.com/datasheets/184%20PIN%20512MB%201G%20Unbuffered%20DDR%20DIMM%20PC3200%20ds.pdf

which works on this board.

ISE FPGA Design Flow Overview

The ISE™ design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click a box in the following figure.

Design Entry

Create an ISE project as follows:

1. Create a project.
2. Create files and add them to your project, including a user constraints (UCF) file.
3. Add any existing files to your project.
4. Assign constraints such as timing constraints, pin assignments, and area constraints.

Functional Verification

You can verify the functionality of your design at different points in the design flow as follows:

• Before synthesis, run behavioral simulation (also known as RTL simulation).
• After Translate, run functional simulation (also known as gate-level simulation), using the SIMPRIM library.

• After device programming, run in-circuit verification.

Design Synthesis

Synthesize your design.

Design Implementation

Implement your design as follows:

1. Implement your design, which includes the following steps:
   • Translate
   • Map

• Place and Route

2. Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:
   • Process properties
   • Constraints
   • Source files
3. Synthesize and implement your design again until design requirements are met.

Timing Verification

You can verify the timing of your design at different points in the design flow as follows:

• Run static timing analysis at the following points in the design flow:

• After Map
• After Place & Route
• Run timing simulation at the following points in the design flow:
  • After Map (for a partial timing analysis of CLB and IOB delays)
  • After Place and Route (for full timing analysis of block and net delays)

Xilinx Device Programming

Program your Xilinx device as follows:

1. Create a programming file (BIT) to program your FPGA.
2. Generate a PROM, ACE, or JTAG file for debugging or to download to your device.
3. Use iMPACT to program the device with a programming cable.

http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/html/ise_fpga_design_flow_overview.htm

Go to the ISE Quick Start Tutorial to get an idea of the additional capabilities of ISE.

http://toolbox.xilinx.com/docsan/xilinx82/books/docs/qst/qst.pdf

Xilinx EDK Tool Flow

MIT FPGA Courses

6.375 Complex Digital Systems

A project-oriented course to teach new methodologies for designing multi-million-gate CMOS VLSI chips using high-level synthesis tools in conjunction with standard commercial EDA tools. The emphasis is on modular and robust designs; reusable modules; correctness by construction; architectural exploration; and meeting the area, timing, and power constraints within standard-cell frameworks. 
　

 6.111 Introduction to Digital Systems

Lectures and labs on digital logic, sequential building blocks, finite-state machines, timing and synchronization, and FPGA-based design prepare students for the design and implementation of a final project of their choice: games, music, digital filters, wireless communications, video, or graphics. Extensive use of Verilog for describing and implementing digital logic designs on a state-of-the-art FPGA. Students engage in extensive written and oral communication exercises. 

The FPGA labkit is a state-of-the-art platform for prototyping digital designs. Based on a 6-million gate platform-scale FPGA, the labkit is designed to facilitate complex and high-performance projects. Several peripheral devices are built into the labkit PCB and hardwired to the FPGA. These include high-speed memory, audio and video encoders and decoders, and other digital interfaces, such as PS/2 and RS-232 ports.

http://web.mit.edu/6.111/www/s2004/NEWKIT/

A brief tutorial on the software used to program the labkit's FPGA with Xilinx ISE is also provided @ http://web.mit.edu/6.111/www/s2004/NEWKIT/ise.shtml.