It seems Sce-Mi has been improved in this version. Sce-Mi, the Standard Co-Emulation Modeling Interface, is an Accellera standard which was designed to aid in verification of hardware designs. The standard specifies a transaction-based modeling interface used to pass messages between an un-timed software test bench and a design under test (DUT) described in register transfer language (RTL). The DUT can be emulated on an FPGA to achieve better performance than software RTL simulators are capable of.
|Bluespec Core Technology|
|Bluespec Compiler (BSC)||Compiles a high-level model, transactor, test bench or implementation into Verilog RTL or SystemC|
|Bluespec Simulator (Bluesim)||Simulates Bluespec designs 5X-20X faster than RTL|
|Bluespec Development Workstation (BDW)||Provides a high-level GUI-based development environment for the design, analysis and debug of Bluespec designs|
|emVM||Provides debug, instrumentation & co-emulation for easy emulation of synthesizable models and legacy RTL with third-party FPGA boards/emulators|
The following links in http://www.bluespec.com/forum/ provide the related documentations:
- The Bluespec Reference Guide is a detailed language reference manual including full documentation for the library packages
- The BSV User Guide describes the mechanics of running the Bluespec tools, from either the development workstation or the command line, including complete descriptions of compiler flags and Bluesim documentation.
- This Bluespec example book teaches the BSV language through small, complete, executable BSV programs. While not an exhaustive reference manual of all BSV features, it describes many of the most commonly used features. A tar file containing all examples in machine-readable form is also provided.
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- This emVM Use Guide document describes Bluespec's emVM environment for implementing software-hardware co-emulation with FPGAs.
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