"Going beyond beyond the functionality of ChipScope Pro, Identify makes is possible to perform the on-chip debug at multiple hierarchical points within the RTL source and to do this without altering the source at all. Identify uses an automated instrumentation technique in order to create and attach sampling, trigger and communication logic into each FPGA forming the prototype as required.
Waveform views such as those seen in the ChipScope Pro logic analyzer are possible, but a significant added bonus is that the samples and triggers are overlaid onto the RTL source code using the same symbolic names as in the RTL. Thus, for example, it is possible to see the actual value of an enumerated type in which a state machine is captured on the FPGA. Triggers may be set in a similar way, using the source name-space. A unique benefit is that triggers can be set for when a particular line of RTL is reached, much like a software engineer would set breakpoints in a program."