Xilinx ISE 12.2

ISE 12.2 is out. It seems "LIT:600 - IOBUFDS symbol" problem was addressed in 12.2. With ISE 12.1, we often got

"LIT:600 - IOBUFDS symbol ... does not have IOSTANDARD specified. Map is unable to generate a default IOSTANDARD for IOBUFDS, one has to be explicitly provided."

which is similar to the one in the Xilinx forum.

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/How-can-I-control-2-DDR2-modules-in-1-FPGA-chip-by-using-MIG-IP/td-p/77267

With ISE 11.5, the above problem was not there.

X-HDL - Verilog VHDL bi-directional translator

X-HDL is an excellent Verilog <=> VHDL bi-directional translator developed by X-Tek, although it seems X-Tek had difficult time before 2005. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, "hand tweaks" of the translated code. X-HDL also contains specialized algorithms which are very effective in translating behavioral-level code to functionally equivalent target-language code.

Key Features

• Provides both GUI and command-line modes
• Performs automatic hierarchical translations as well as file-at-time translations.
• Translates structural, RTL and behavioral code
• Preserves comments with placement nearly identical to the source
• Consistent code formatting with user customizations
  • VHDL'87 or VHDL'93 syntax generation
  • Verilog-2001 syntax generation
  • Code alignment controls
  • Indentation controls
  • Line wrap controls
• Supports component libraries
• Smart overloaded subprogram handling
• Intelligently determines if translated Verilog tasks/functions are local or global within the VHDL.
• VHDL conversion function filtering
• Conversion definitions to support user-defined translation
• Support for pre- and post-processing scripts to enable user-specific translation needs.

The current version is X-HDL 4.1.4.For more detail information, please see

http://www.x-tekcorp.com/docs/xhdl4/X-HDL.pdf

Other this kind of tools include v2v.

Identify RTL Debugger Tutorial

Identify is an excellent software tool that enables users to probe and debug FPGA designs directly in the source RTL, working with Synplify synthesis tool.

According to FPGA-Based Prototyping - "Productivity to Burn" by Lee Hansen (Xilinx) and Doug Amos (Synplicity):

"Going beyond beyond the functionality of ChipScope Pro, Identify makes is possible to perform the on-chip debug at multiple hierarchical points within the RTL source and to do this without altering the source at all. Identify uses an automated instrumentation technique in order to create and attach sampling, trigger and communication logic into each FPGA forming the prototype as required.

Waveform views such as those seen in the ChipScope Pro logic analyzer are possible, but a significant added bonus is that the samples and triggers are overlaid onto the RTL source code using the same symbolic names as in the RTL. Thus, for example, it is possible to see the actual value of an enumerated type in which a state machine is captured on the FPGA. Triggers may be set in a similar way, using the source name-space. A unique benefit is that triggers can be set for when a particular line of RTL is reached, much like a software engineer would set breakpoints in a program."

A good training of Identify RTL Debugger is

http://klabs.org/richcontent/MAPLDCon03/presentations/p/p4_beards_s.ppt

A good tutorial of Identify is

http://www.actel.com/documents/IdentifyAE_Tutorial_UG.pdf

http://www.actel.com/documents/IdentifyAE_QS_UG.pdf

With this tool, debugging is much more easy as it is done at the RTL level, comparing to Chipscope.

Comparison Between Veritak and Modelsim

Veritak is a Verilog HDL Compiler/Simulator that supports the major Verilog 2001 HDL features. It provides an integrated environment, which includes a VHDL to Verilog translator, a syntax highlighting editor (called Veripad), a class hierarchy viewer, a multiple-waveform viewer capable of handling a gigabyte vcd files, source analyzer, and more -- it is available for Windows XP/2000/2003/Vista32/Vista64/Windows7 32bit/64bit.. The latest version is 3.80a.

Veritak had compared Veritak1.71/1.82A/3.00A( Released .) and MXE6.0d(Not Starter. Full Xilinx Edition of Modelsim) in 2006 and claimed 2x performance to MXE.

We tested with Veritak 3.80a and Modelsim SE 6.6b and saw Veritak still is much faster. Veritak costs $50 - $270, while Modelsim license costs > $1000. However, possibly Veritak is only good for a small project.

2010 Video Codec Comparison

In

http://compression.ru/video/codec_comparison/h264_2010/msu_mpeg4_avc_h264_codec_comparison_2010_short.pdf

DivX H.264, Elecard H.264, Intel® MediaSDK AVC/H.264, MainConcept H.264, Microsoft Expression Encoder, Theora, x264 and XviD (MPEG-4 ASP codec) were compared.

Analysis of all tested sequences yields the following codec rankings:

1. x264

2. x264 with psycho-visual enhancement

3. DivX H.264

4. MainConcept

5. Elecard

6. DivX ASP

16th June 2010: Appendix with VP8 encoder analysis is released.

http://compression.ru/video/codec_comparison/h264_2010/appendixes.html#Appendix_8

VP8 Codec Coming To FFmpeg ?

http://developers.slashdot.org/story/10/06/28/1120200/VP8-Codec-Coming-To-FFmpeg