Monday, January 19, 2009
Video surveillance market poised for explosive growth
http://www.securityinfowatch.com/article/article.jsp?siteSection=321&id=14777&pageNum=1
ABI Research believes that the video surveillance market is poised for explosive growth, which the firm forecasts to expand from revenue of about $13.5 billion in 2006 to a remarkable $46 billion in 2013.
IP Video Surveillance Market Grows 48% in 2007
SCOTTSDALE, Ariz., April 22, 2008—MultiMedia Intelligence reports that the market for IP/Networked video surveillance cameras grew nearly 50% in 2007, to approach $500 million worldwide. This growth is nearly four times the growth rate of the broader video surveillance equipment market, which also includes CCTV cameras, Digital Video Recorders (DVRs) and Network Video Recorders (NVRs), and IP Encoder/Streamers.
While IP/networked video surveillance camera units and revenue are growing rapidly, they remain a small percentage of the overall surveillance market. The outlook for continued growth of IP/Networked video surveillance is strong. However, the barriers to it overtaking traditional CCTV surveillance will prove enduring.
“The transition from traditional CCTV surveillance to networked digital surveillance is revolutionary for the physical security industry, according to Mark Kirstein, President of MultiMedia Intelligence. “Yet this transition is also seen as over-hyped and under-performing compared to many expectations. Both are true.”
MultiMedia Intelligence’s new research also found:
- IT-oriented companies such as Cisco and EMC are adding a new competitive dynamic. Focused surveillance competitors, such as Axis Communications, IndigoVision, March Networks, Nice Systems and Verint, are leveraging the growth of IP/networked surveillance to take on the legacy surveillance equipment manufacturers. The new competitive environment is drastically accelerating product innovation.
- Growth in the DVR market overall is slowing. Network video recorders, both hardware-based and software-based, are emerging as the key growth category.
- The semiconductor opportunities in DVRs and IP/networked surveillance equipment are strong. Companies, such as Texas Instruments and Techwell, have established a strong position in their respective segments. A variety of competitors including Analog Devices, Aptina, NextChip, OmniVision, PentaMicro, Pixim, and Stretch are positioning themselves in the key growth categories of video processing/Codecs and image sensors.
- With strong expertise in physical security, the legions of dealers and VARs are generally not experts in networking and IP technology. This lack of expertise is a major barrier to adoption of networked video among end users.
“Internet Protocol (IP)/Networked Video Surveillance Market: Equipment, Technology & Semiconductors” analyzes the IP/Networked surveillance market within the context of the broader video surveillance industry. The research examines the value chain from end-users to distribution/sales, integrators, equipment manufacturers, software vendors, and semiconductor providers. Our expertise is based on years of researching the physical security, digital camera and semiconductor markets. The report forecasts and segments markets by product category, including CCTV & IP cameras, Encoder/Streamers, DVR/NVR, and surveillance software & video content analytics. In addition, detailed technology segmentation and forecasts are included for semiconductors in each product category, video signal processors & codecs, image sensors (CMOS/CCD), camera resolution, and network interfaces (PoE, Wi-Fi/Mesh, others). Forecasts include units, revenue, ASPs at the equipment, software and semiconductor level by product type. About MultiMedia IntelligenceMultiMedia Intelligence provides actionable intelligence on the markets and technologies for delivering IP video to the Nth screen. With a broad "ecosystem-based" perspective that moves beyond the classic 'three screens' of TVs, mobile handsets, and computers, we identify the opportunities in enabling and monetizing digital media on a multi-platform, multi-network basis.
Maxim Buys Mobilygen
SCOTTSDALE, Ariz., October 16, 2008— Maxim Integrated Products announced earlier this week an agreement to acquire Mobilygen, a privately held, fabless semiconductor company targeting the video surveillance semiconductor market. This acquisition brings Maxim into a fast growing semiconductor segment, as video surveillance equipment transitions from traditional CCTV cameras to IP-based digital cameras. |
The opportunity for semiconductors in video surveillance is driven by both top-line unit growth in the surveillance market, as well as an on-going shift to digital and networked video surveillance. The trend toward IP-based video surveillance equipment ushers in an innovation and technology race that favors sustained semiconductor value.
Mobilygen Positioning
Mobilygen is focused on advanced H.264 codec technology, targeted at video surveillance through its ASSP (application specific standard product). Their MG3500 HD SOC supports HD resolution video and includes the codec and a host processor. The MG2500 SD SOC is similar, but targets standard definition video. Combining the host processor with support for multiple video stream codecs, the devices are oriented toward the surveillance digital video recorder (DVR) market. Their MG1262-SD codec eliminates the host processor, making it more applicable for IP cameras.
Video Processors & Codecs in Surveillance
The video processor is one of the key semiconductor devices in both the camera market and the DVR market. The primary function of the video processor is to compress/decompress the digital video and implement the codec algorithms. MPEG-4 has quickly become a mainstream codec standard for digital surveillance video. However, rather than replacing MJPEG (Motion JPEG), the MPEG-4 standard is becoming a dual codec in combination with MJPEG. The H.264 standard is the next generation MPEG-4 codec and is already emerging in the market. A next-generation codec, the Scalable Video Codec (SVC), is on the horizon. As the name implies, SVC is designed to support the video requirements of multiple applications in a single codec. The video processor also performs image processing and implements video content analytics in advanced systems. There are three primary implementations for the video processors:
- ASIC – Customer-specific video processor/codec implementation
- DSP – Multi-application, software programmable processor/codec
- ASSP – Function-specific processor/codec offered to multiple equipment level manufacturers
Fierce Competition in the Emerging Market
The video processor/codec market is becoming more competitive as many processor, ASSP and DSP companies across the semiconductor market have identified the strong video surveillance opportunity. Texas Instruments has the dominant position in this market. Yet, many companies are positioning to challenge their position. Among them include Analog Devices, Ambarella, Faraday, Freescale, HiSilicon, NextChip, PentaMicro, Stretch, Stream Processors, and of course… Mobilygen, now Maxim.
This Intelligence brief is based on MultiMedia Intelligence’s recent research, “Internet Protocol (IP)/Networked Video Surveillance Market: Equipment, Technology & Semiconductors”. The report analyzes the IP/Networked surveillance market within the context of the broader video surveillance industry. The research examines the value chain from end-users to distribution/sales, integrators, equipment manufacturers, software vendors, and semiconductor providers. Our expertise is based on years of researching the physical security, digital camera and semiconductor markets.
The report forecasts and segments markets by product category, including CCTV & IP cameras, Encoder/Streamers, DVR/NVR, and surveillance software & video content analytics. In addition, detailed technology segmentation and forecasts are included for semiconductors in each product category, video signal processors & codecs, image sensors (CMOS/CCD), camera resolution, and network interfaces (PoE, Wi-Fi/Mesh, and others). Forecasts include units, revenue, ASPs at the equipment, software and semiconductor level by product type.
Friday, January 16, 2009
Forte Cynthesizer
Cynthesizer generates production-quality RTL using a high-level SystemC-TLM design description as input. Cynthesizer makes high-level design practical by accelerating architecture exploration and providing the fastest path to silicon-proven RTL.
Cynthesizer provides an open and customizable environment based on standard languages and APIs. It integrates a complete tool chain that includes leading EDA products, accelerating the adoption of ESL design and reducing the cost of deployment.
Wednesday, January 14, 2009
SystemC
About SystemC
http://www.systemc.org/community/about_systemc/
The Language for System-Level Modeling, Design and Verification
Ratified as IEEE Std. 1666™-2005, SystemC™ is a language built in standard C++ by extending the language with the use of class libraries. SystemC addresses the need for a system design and verification language that spans hardware and software. The language is particularly suited to model system's partitioning, to evaluate and verify the assignment of blocks to either hardware or software implementations, and to architect and measure the interactions between and among functional blocks. Leading companies in the intellectual property (IP), electronic design automation (EDA), semiconductor, electronic systems, and embedded software industries currently use SystemC for architectural exploration, to deliver high-performance hardware blocks at various levels of abstraction and to develop virtual platforms for hardware/software co-design.
Why SystemC?
An SoC is literally a system on a chip, consisting of both silicon and embedded software. Its design involves complex algorithm and architecture development and analysis similar to that performed in system design – a trade-off process that determines critical metrics, such as SOC performance, functionality, and power consumption.
Consequently, design tools must deliver orders-of-magnitude improvement in productivity at both architectural and implementation (RT and physical) levels. Moreover, tools must support a methodology that enables the early development of embedded application and system software, long before the availability of the RTL design or silicon prototype. Failure to achieve the requisite improvements in design productivity would result in missed market windows, and exploding design costs.
SystemC is a single, unified design and verification language that expresses architectural and other system-level attributes in the form of open-source C++ classes. It enables design and verification at the system level, independent of any detailed hardware and software implementation, as well as enabling co-verification with RTL design. This higher level of abstraction enables considerably faster, more productive architectural trade-off analysis, design, and redesign than is possible at the more detailed RT level. Furthermore, verification of system architecture and other system-level attributes is orders of magnitude faster than that at the pin-accurate, timing-accurate RT level.
The SystemC community consists of a large and growing number of system design companies, semiconductor companies, intellectual property providers, and EDA tool vendors who have joined together to support and promote the standard.
System Design with SystemC
Wednesday, January 7, 2009
HD Video Conference Systems
2. Telepresence Company of the Year 2008 - Cisco TelePresence
3. Video-enabled Unified Communications Company of the Year 2008 - RADVISION
4. Most Innovative Videoconferencing Product of the Year 2008 - Aethra Electra roll-about, High Definition videoconferencing system
5. Industry Leader of the Year 2008 - Fredrik Halvorsen, CEO of TANDBERG since December 2005
The Editor's Choice of "The 10 Best New Video Conferencing Systems of the Year 2006" is
Monday, January 5, 2009
Cadence C-to-silicon compiler
(07/14/2008 8:38 AM EDT)
C-to-Silicon Compiler is the first product delivered from a new initiative codenamed Sydney and was developed within an internal incubation group headed by Michael McNamara, vice president/general manager, C-To-Silicon Compiler. The product aims are twofold: to bridge the gap between the use of C as a design language and RTL description of the design, and to improve the silicon implementation of the design by providing a direct link between manufacturing constraints and the C description.
The new product is not meant to compete with custom design projects, explains Ran Avinun, marketing group director, System Design and Verification, which must take advantage of specific optimizations available only with the use of existing tools and methods. By focusing just on IP meant for re-use, the new tool can provide good quality of results while saving the time required to optimize the design through the use of traditional Hardware Description Languages (HDL).
2. The flow and methodology enabled by C-to-Silicon Compiler.
Figure 1 shows the flow and methodology enabled by C-to-Silicon Compiler. The Technology Library and Design Constraints are input separately from the source code of the design, enabling easier retargeting. The synthesis capability is provided by the Encounter RTL Compiler engine which is embedded in the tool. Mr. McNamara explained that the use of the proprietary Cadence synthesis engine does not prohibit engineers from taking the output of the new tool at the RTL format and use another third party synthesis tool to complete the production of a manufacturing ready design. In this way Cadence is not limiting the market of the new offering to just its own customers base, claims Mr. Avinun.
According to Mr. McNamara in addition to the capabilities already described, the new tool incorporates technology that enables parallel optimization of control and datapath logic, incremental synthesis for faster Engineering Change Order (ECO) handling, and generates Fast Hardware Models (FHM) that accelerate verification when the design team uses the Incisive Verification tool from Cadence. Although the FHM models are designed to meet the OSCI TLM 1.0 specification, and are scheduled to be updated to the just released 2.0 standard, they do also take advantage of Cadence's proprietary technology and are therefore, not usable with third party simulators.
For designers interested in verifying the equivalence of the C and RTL descriptions of the design, the new tool offers a direct integration with the SLEC product from Calypto.
The Cadence C-to-Silicon Compiler is available now in limited production. C-to-Silicon Compiler will be demonstrated during the DA SHOW/CDNLive! conference starting July 17.
Precision Synthesis Tool
http://www.mentor.com/products/fpga_pld/synthesis/
Products
- Precision RTL
Intuitive logic synthesis environment with advanced optimization techniques, award-winning timing analysis, and advanced inferencing technology. Precision RTL enables vendor-independent design, accelerates time to market, eliminates design defects and delivers superior quality of results (QoR).
Precision RTL Plus
Precision RTL Plus is the latest addition to the Precision Synthesis family of products which builds on Precision RTL by delivering a vendor-independent solution for breakthrough productivity. Precision RTL Plus provides three industry-first capabilities for every designer, regardless of level of expertise, to reach timing closure faster, minimize the impact of late cycle design changes and make efficient use of FPGA architectural blocks.- Precision Physical
All of the capabilities of Precision RTL with advanced physical synthesis environment offering interactive placement optimization capabilities for complex FPGA designs that enhances FPGA designer productivity and allows rapid timing convergence. Precision Physical offers a powerful Placement Reuse/ECO feature allowing incremental changes that preserve timing constraints and maintain predictable results.
A tutorial can be found @
http://vlsilab.fiu.edu/projects/Precision_Tutorial/Precision_Tutorial.pdf
Thursday, January 1, 2009
FPGA vs ASIC
http://www.eetimes.com/showArticle.jhtml?articleID=47101995
A comparison between FPGA and ASIC was given by Kuon and Rose in 2006 It also presented empirical measurements quantifying the gap between FPGAs and ASICs. It was observed that for circuits implemented entirely using LUTs and flip-flops (logic-only), an FPGA is on average 40 times larger and 3.2 times slower than a standard cell implementation. An FPGA also consumes 12 times more dynamic power than an equivalent ASIC on average. It was confirmed that the use of hard multipliers and dedicated memories enable a substantial reduction in area and power consumption but these blocks have a relatively minor impact on the delay differences between ASICs and FPGAs.
A good discussion about difference of FPGA vs ASIC can be found at
http://vlsifaq.blogspot.com/2007/11/what-is-difference-between-fpga-and.html
where also gave some useful links:
http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm
http://www.soccentral.com/results.asp?CategoryID=488&EntryID=15887