TI Netra Is Out - DM8168

New TMS320DM8168 DaVinci™ Video Processor

http://www.ti.com/ww/en/dsp/davinci-netra/index.shtml

Offering best-in-class embedded video performance for video surveillance and video communications DM8168 Based DVR System Block Diagram DM8168 Based Video Communications System Block Diagram TI’s new TMS320DM8168 device offers best-in-class embedded video performance for video surveillance and communications applications enabling 4X video performance at higher quality and lower bitrates. TMS320DM8168 system-on-chip (SoC) consolidates all of the capture, compression, display and control functionalities of an HD multi-channel system onto a single chip and sets industry benchmark performance to reduce cost and design complexity. Benefits of TMS320DM8168 DaVinci Video Processor: Reduce system electronic bill of materials (eBOM) costs by 50 percent Reduce board area and power consumption with DM8168 SoC - replaces more than 10 discrete complements Increase multi-channel density and support for higher resolutions Enable higher quality video at lower bitrates Utilize comprehensive codec support including H.264, MPEG-4 and VC1 at HD resolutions Simultaneously support 3 channels of 1080p at 60 fps Reduce glass-to-glass latency below 50 ms Leverage multiple interfaces including gigabit Ethernet, PCI Express, SATA2, DDR2, DDR3, USB 2.0, MMC/SD, HDMI and DVI Seamlessly capture up to 16 D1 video channels DM8168 Based DVR System Block Diagram Enlarge The innovative DM8168 video SoC slashes digital video recorder (DVR) system cost and complexity by providing simultaneous 16 channels of H.264 high profile D1 encoding with CIF multi-streaming and eight channels of D1 decoding plus video compositing and graphics blending supporting up to three independent displays. DM8168 Based Video Communications System Block Diagram Enlarge For video communications applications, ability to simultaneously support three channels of 1080p at 60 frames per second (fps) and reduce glass-to-glass latency below 50 milliseconds (ms) by eliminating off-chip inefficiencies with codec latency of less than 1 ms.