Friday, September 25, 2009

Matlab Simulink and HDL

Simulink HDL Coder 1.6

Generate HDL code from Simulink models and MATLAB code


You can use Simulink to model your system and then automatically generate bit-true, cycle-accurate, synthesizable Verilog and VHDL code and test benches.

Simulink® HDL Coder™ generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink® models, Stateflow® charts, and Embedded MATLAB™ code. The automatically generated HDL code is target independent.

The Simulink HDL Coder product generates Verilog code that complies with the IEEE 1364-2001 standard and VHDL code that complies with the IEEE 1076 standard. As a result, you can verify the automatically generated HDL code using popular functional verification products, including Cadence® Incisive®, Mentor Graphics® ModelSim®, and Synopsys® VCS®. You can also map the automatically generated HDL code into field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) using popular synthesis tools, such as Altera® Quartus® II, Cadence Encounter® RTL Compiler, Mentor Graphics® Precision®, Synopsys Design Compiler®, Synplicity® Synplify®, and Xilinx® ISE™.

Simulink HDL Coder also generates HDL test benches that help you verify the generated HDL code using HDL simulation tools.

Charles Fulks at Intuitive Research and Technology gives example codes in

http://www.irtc-hq.com/fpga.php



Embedded Systems Conference example files
File

esc_sv09.mdl
esc_sv09_init.m
esc_sv09_pwm_pkg.m
esc_sv09_sin_pkg.m
esc_sv09_stop.m
esc_sv09_fpga.do
esc_sv09_fpga_tb.vhd
tb_utilities_pkg.vhd
esc_sv09_fpga.vhd
esc_sv09_pwm.vhd
esc_sv09_pwm_pkg.m
esc_sv09_sin.vhd
esc_sv09_sin_pkg.vhd
Description

Simulink model
Matlab script
Matlab script
Matlab script
Matlab script
ModelSim script
VHDL Testbench
VHDL Testbench package
VHDL Top Level Design
VHDL PWM Design
VHDL PWM Package (generated by Matlab script)
VHDL PWM Design
VHDL PWM Package (generated by Matlab script)


His model based FPGA design principle can be seen at

http://sedware.com/sites/default/files/FPGA_Introduction.pdf

http://sedware.com/sites/default/files/VHDL.pdf

1 comment:

enliteneer said...

Is there any tutorial or book that shows how to get started using mathworks simulink/xilinx system generator for a simple video application?

Not sure if video IPs even come with system generator, but I would love to learn the design flow for doing video applications (YCbCr to
RGB, image rotation, or basically any video processing).

Thanks!

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