Matlab Simulink and HDL

Simulink HDL Coder 1.6

Generate HDL code from Simulink models and MATLAB code

Simulink® HDL Coder™ generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink® models, Stateflow® charts, and Embedded MATLAB™ code. The automatically generated HDL code is target independent.

The Simulink HDL Coder product generates Verilog code that complies with the IEEE 1364-2001 standard and VHDL code that complies with the IEEE 1076 standard. As a result, you can verify the automatically generated HDL code using popular functional verification products, including Cadence® Incisive®, Mentor Graphics® ModelSim®, and Synopsys® VCS®. You can also map the automatically generated HDL code into field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) using popular synthesis tools, such as Altera® Quartus® II, Cadence Encounter® RTL Compiler, Mentor Graphics® Precision®, Synopsys Design Compiler®, Synplicity® Synplify®, and Xilinx® ISE™.

Simulink HDL Coder also generates HDL test benches that help you verify the generated HDL code using HDL simulation tools.

Charles Fulks at Intuitive Research and Technology gives example codes in

http://www.irtc-hq.com/fpga.php

Embedded Systems Conference example files
File esc_sv09.mdl esc_sv09_init.m esc_sv09_pwm_pkg.m esc_sv09_sin_pkg.m esc_sv09_stop.m esc_sv09_fpga.do esc_sv09_fpga_tb.vhd tb_utilities_pkg.vhd esc_sv09_fpga.vhd esc_sv09_pwm.vhd esc_sv09_pwm_pkg.m esc_sv09_sin.vhd esc_sv09_sin_pkg.vhd	Description Simulink model Matlab script Matlab script Matlab script Matlab script ModelSim script VHDL Testbench VHDL Testbench package VHDL Top Level Design VHDL PWM Design VHDL PWM Package (generated by Matlab script) VHDL PWM Design VHDL PWM Package (generated by Matlab script)

His model based FPGA design principle can be seen at

http://sedware.com/sites/default/files/FPGA_Introduction.pdf

http://sedware.com/sites/default/files/VHDL.pdf

Harmonic's HD Encoder

Altera's Stratix III FPGAs Chosen for Harmonic's Next-Generation Universal Broadcast Video Encoder

San Jose, Calif., April 20, 2009—Altera Corporation (NASDAQ: ALTR) today announced that Harmonic has chosen its Stratix® III FPGAs for its next-generation high-definition (HD) H.264 1080p video broadcast encoder. Delivering the right combination of performance, programmability, flexibility and low power consumption, the Stratix III devices help Harmonic to improve video quality while consuming significantly less bandwidth.

Altera® Stratix III devices are used in Harmonic's DiviCom Electra 8000, the world's first encoding and transcoding platform to support MPEG-4 AVC (H.264) and MPEG-2 CODECs in standard-definition (SD) and HD formats up to full frame-rate 1080p 50/60. While helping to provide superior picture quality, Altera's Stratix III devices also contribute to the Electra 8000&'s ground-breaking energy efficiency.

“Harmonic's DiviCom Electra 8000 sets the benchmark for real-time video-processing technology,” said Nimrod Ben-Natan, Vice President of Product Marketing, Solutions and Strategy for Harmonic Inc. “Altera's Stratix III FPGAs help us enhance our video algorithms. Altera offers clear FPGA leadership in digital signal processing (DSP) and external memory performance, while still delivering low power requirements.”

“Altera has made significant investments in our FPGA architecture and solutions to meet the demanding requirements of 1080p video-processing applications,” said Arun Iyengar, senior director of Altera's broadcast and communications business units. “Altera's Stratix III FPGAs deliver twice the video-processing capability of previous-generation FPGAs while maintaining a constant power budget. This allows broadcast leaders like Harmonic to further differentiate its products.”

H.264 Soft Encoder Comparison

H.264 Predefined profiles

H.264 Profile Level

IBC 2009: Tandberg Unveils HD H.264

http://webcast.broadcastnewsroom.com/articles/viewarticle.jsp?id=842482&afterinter=true

IBC 2009: Tandberg Unveils Next-Generation MPEG-4 Gear

Shows complete contribution system

By Glen Dickson

IBC Amsterdam 2009: Complete Coverage of the IBC Show

Ericsson unit Tandberg Television introduced at IBC new MPEG-4 encoding products aimed at both backhauling high-definition signals and distributing them directly to consumers.

According to Tandberg VP of technology Matthew Goldman, Tandberg is the only vendor to provide a complete MPEG-4 AVC HD 4:2:2 system solution for the C&D (Contribution and Distribution) market, i.e. either backhauling signals from live events or distributing high-quality mezzanine feeds to cable headends which will then be re-compressed for delivery to the home. It was demonstrating the system in its joint Tandberg/Ericsson booth.

The new MPEG-4 4:2:2 system, which uses 10-bit video processing for improved color gradation, supports HD encoding up to the 1080p/60 format. It includes the existing Tandberg RX8200 receiver, which can be upgraded to support 4:2:2 10-bit encoding through a software option. Goldman expects the 4:2:2 system will eventually be used to backhaul feeds produced in the 1080p/60 format at bit-rates ranging from 20 to 80 Mbps.

"That's in the sweet spot that JPEG2000 can't hit," says Goldman.

Tandberg also introduced the EN8190 HD encoder, an MPEG-4 4:2:0 product aimed at direct-to-home (DTH) satellite applications as well as the IPTV market. Goldman says the EN8190 represents a 20-25% improvement in bit-rate efficiency over the company's previous MPEG-4 4:2:0 model, enough for a DTH operator to add one more HD channel per satellite transponder. Tandberg was demonstrating the EN8190 delivering six HD channels in 30 Mbps of bandwidth using its statistical multiplexing technology.

In another part of its booth, Tandberg was explaining how its OpenStream VOD management system can be used today to support multi-platform delivery. The demonstration showed how a VOD movie that was being delivered to a basic Motorola DCT-2000 set-top box could be paused, with the movie then being restarted as streaming video delivered to an Apple iPhone over a Wi-Fi link.

Tandberg VP of applications software strategy Michael Adams says the company will give a more in-depth demonstration of OpenStream's multiplatform capabilities at the SCTE show in Denver next month. He says the streaming form of VOD could be delivered just as easily over a wireless 3G network as over a Wi-Fi link.

"That's just a plumbing issue," says Adams, who expects that Tandberg will be involved in a commercial deployment of such multi-platform delivery by early next year.

Broadcasting & Cable Copyright © 2008 Reed Business Information A division of Reed Elsevier Inc. All rights reserved.

Verilog Primer

http://www.verilogtutorial.info/ Chapter1: Introduction to Verilog hardware description language Chapter 2: Verilog Structure 2.1 Modules 2.2 Structural Design with Gate Primitives and the Delay operator 2.3 Structural Design with Assignment Statements 2.4 Structural Design with using Modules 2.5 Behavioral Design with Initial and Always blocks Chapter 3: Verilog Syntax Details 3.1 Structural Data Types: wire and reg 3.2 Behavioral Data Types: integer, real, and time 3.3 Number Syntax 3.4 Behavioral Design with blocking and non-blocking statements 3.5 Arrays, Vectors, and Memories 3.6 Operators Chapter 4: Verilog Design Flow Step 1: Create RTL Design Models and Behavioral Test Bench Code Step 2: Functionally Simulate your Register-Transfer-Level Design Step 3: Convert RTL-level files to a Gate-level model with a Synthesizer Step 4: Perform Gate Level simulations with FPGA or ASIC libraries Optional Step: Gate-level simulation with SDF timing information

Info site for timing diagrams

Aptina 1080p CMOS Sensor

It is called MT9J001. The detail info need to be viewed under NDA. The following is their press release.

http://www.micron.com/about/news/pressrelease.aspx?id=99025FDDEFA2B68E

San Jose, CA and Cologne, Germany , Tuesday, September 23, 2008 – Continuing to push the capabilities of high performance CMOS image sensors, Aptina Imaging, today introduced its new 10-megapixel (part number MT9J001) sensor for digital still camera, digital video and hybrid camera applications. The sensor provides camera manufacturers with an easy to integrate, unique sensor that combines rapid image capture and superior image quality. The new 1.67-micron pixel sensor features 1/2.3” optical format, and a parallel/serial frame rate of 7.5fps (parallel) and 15fps (serial). It is the first 10MP CMOS image sensor for point-and-shoot digital cameras and the first product to integrate Aptina’s High-Speed Serial Pixel Interface (HiSPi™). This high bandwidth serial interface is based upon the JEDEC SLVS signaling standard and enables faster data transfer rates (up to 2.8 Gbps). Aptina’s new sensor features HiSPi™ and allows a camera to capture and process data in HD (1080p/60fps). Additionally, the new 10MP sensor is the first of Aptina’s high performance sensors with digital re-sampling after binning. This re-sampling feature removes binning artifacts seen in 2x2 binned images and matches the distribution density of the original unbinned image. As a result of the extended binning capabilities of the sensor, camera users have a full field of view in HD, enhancing the overall end-user experience. Aptina’s announcement comes as the Photokina 2008 international tradeshow in Cologne, Germany begins.

"Aptina CMOS technology is advancing rapidly, enabling us to create high performance camera products for our global customers," says Sandor Barna, Vice President of Marketing at Aptina. "Our new 10MP image sensor incorporates a unique 1.67-micron pixel format and a four-lane HiSPi™ serial data interface to achieve results unmatched by CCD technology such as 60 fps HD video capture at 1080p."

HiSPi™ is the High Speed Serial Pixel Interface developed and owned by Aptina Imaging. The open access, scalable technology enables 1080p/60 fps performance (and beyond) and has been adopted by many of Aptina’s business partners to meet the challenges of high speed, low power consumption data transfer. HiSPi™ technology provides distinct benefits for users including open access to a performance focused interface, the ability to support 1080p/60fps today—4X the data rate of standard broadcast (DI)—and the scalability to accommodate higher data rates for the future. The MT9J001 10MP image sensor extends Aptina’s portfolio of higher resolution products, providing increased image quality and HD video capture like the 5MP (MT9P001), 8MP (MT9E001), and 9MP (MT9N001). Samples will be available in 4Q08 and limited production begins in 1Q09.

Omnivision 1080p CMOS Sensor

The OV2710 is a true full HD (1080p) CMOS image sensor designed specifically to deliver high-end HD video to digital video camcorders, notebooks, netbooks, PC webcamand other mobile applications. The 1/3-inch OV2710 addresses the fast growing demand for affordable, HD-quality digital video solutions for video conferencing and recording.

The OV2710 is among the very first no-compromise full HD (1080p) sensors available on the market, meaning it offers the HD video format with a display resolution of 1920 x 1080 pixels, operating at 30 frames per second. Built with OmniVision's proprietary 3 μm OmniPixel3-HS™ high sensitivity pixel technology, the OV2710 delivers low-light sensitivity of 3300 mV/lux-sec, dark current of 6 mV/sec and a peak dynamic range of 69 dB. This enables cameras to operate in virtually every lighting condition from bright daylight to nearly complete darkness below 15 lux.

The OV2710 supports multiple platform architectures and controllers with both parallel and MIPI interfaces. By allowing system designers to leverage the same opto-electrical design across various products and multiple market segments, the OV2710 significantly reduces product development time. OmniVision's OmniPixel3-HS pixel technology has already been proven in high quality webcam/video applications and is now available in 1080p full HD in the OV2710.

DaVinci HD and Netra

The following TI paper reveals Netra, a new TI HD chip?

http://focus.ti.com/asia/download/TechDay09tw_DaVinci_track_3_TVP5158_Brain_Lin_TI.pdf