Formality

Formality is a tool from Synopsys, which is used for Formal Verification. Formal verification is a method to verify two designs without runningsimulations that they are functionally equivalent. Of course one design is the 'reference' design, which is supposed to be a 'good' design, and the second design which is called implementation design, is what is sought to match the 'reference' design.

Usually two kinds of verification are common using formality

1. RTL(ref) vs Netlist(impl)
2. Netlist vs Netlist

For more info how to use Formality, go to

http://www.vlsiip.com/formality/