FPGA projects dominate ASIC by a 30 to 1 margin

Gartner: ASIC design starts to fall by 22% in '09

Dylan McGrath
EE Times 
(03/30/2009 3:01 AM EDT)

SAN FRANCISCO—FPGAs are displacing ASICs—a trend that in 2009 will be exacerbated by the global financial crisis—and now have a 30-to-one edge in design starts, according to market research firm Gartner Inc.

ASIC design starts are expected to drop by 22 percent in 2009 as the economy causes firms to push out and—in some cases—cancel designs, Gartner (Stamford, Conn.) said.

ASIC design starts—completed designs that have taped out—fell 9.5 percent in 2008, according to Gartner. The firm said the financial crisis started to take its toll on ASIC design starts in the fourth quarter of 2008 in the form of push-outs of design projects into 2009.

Since most ASIC vendors have a design cancel fee, there will likely be no word of them being canceled, Gartner said. But just how many of these designs will never go forward is a key question, the firm said.

"More likely, we will see a large percentage of these questionable designs not hit any production and die a slow death by indefinite push-outs," wrote Gartner analyst Bryan Lewis in a report dated Monday (March 30).

New ASIC design starts have been dropping in numbers for years due to system integration, rising design costs, and other types of devices, such as FPGAs or application-specific standard products, taking the socket, Gartner said.

At a product launch event in February, Xilinx Inc. president and CEO Moshe Gavrielov presented data on the trend of declining ASIC starts. Gavrielov spoke of a "programmable imperative," when, he said, FPGAs will dominate for many applications while traditional gate arrays and structured arrays are relegated to high-volume tasks.

Gavrielov argued that factors such as the technological evolution of the FPGA and economic factors such as the rising cost of photomasks make FPGAs the attractive choice for all but the most high-volume applications.