HDfpga

Thanks to a host of technology and market drivers, FPGAs continue to grow in acceptance. Skyrocketing mask costs continue to drive ASIC opportunities to FPGAs, and today’s FPGA manufacturers are leading the push to nanometer technology. As a result, FPGA suppliers are now seeing million-unit orders that were unheard of only a few years ago. Additionally, I/O limitations have helped to level the playing field for FPGAs. Because I/Os are not scalable, they are determining the die size, causing the metric to shift from cost per gate to cost per I/O. With a focus on cost per I/O, the ASIC loses its cost advantages. While ASICs will continue to dominate the shrinking high-performance, high-density market, FPGAs will take a larger share of the mainstream custom logic market. As more ASIC designers choose FPGAs, they will look to development tool vendors to develop and upgrade tools that meet their demanding requirements and their key concerns of timing closure and verification.

Until recently, FPGA design tools were extremely difficult to use and involved learning design flows that were completely different from traditional ASIC design. During the early years of the FPGA industry, synthesis mapping technology was non-existent for LUT (Look Up Table)-based FPGAs, and the primary form of design entry was schematics. Actel, one of the FPGA vendors promoting an ASIC-like design methodology, got initial synthesis support from Synopsys, and as support for language-based design entry grew, the EDA industry saw the birth of FPGA synthesis tools from Synplicity, Mentor Graphics and Synopsys.

Over the years, some FPGA suppliers have also acquired their own synthesis technology and offer it through their software tool suites. FPGA designers can now get an entire design suite containing a rich set of tools for synthesis, physical synthesis, simulation, floorplanning, physical placement and routing, timing analysis and in-circuit debugging for as little as $2,500. This would be a dream in the ASIC world.

FPGA designers used to create designs with the intent of validating them directly on the FPGA devices as illustrated in Figure 1. While this flow seems to work well for designs targeting smaller FPGA devices, the trend is changing. The availability of large FPGAs has ASIC designers turning to them as production solutions and not just for prototyping.

Emerging Challenges

Today, FPGA tools resemble those used in ASIC design, including synthesis, physical synthesis, planning and analysis and verification. However, ASIC designers transitioning to FPGA design will initially be shocked by the simplicity of the FPGA tools. One designer commented, "I can iterate through a design and get it to work on the FPGA in a single day."

Still an FPGA tool flow is not quite as clean as an ASIC flow, and FPGA tools may not have all the features an ASIC designer is familiar with. The FPGA design methodology closest to an ASIC design flow is the flow used to design radiation-tolerant non-volatile FPGAs for military and aerospace applications. Since these devices are expensive one-time programmable (OTP) devices, designers must take extra care to ensure that the design is properly validated before being programmed.

Because the goal is to get the design done right the first time, designers must verify the design at every stage—functional verification at source, functional verification after synthesis, extensive timing analysis along with timing-based simulation through post-layout SDF and finally debugging after programming. The primary concerns of designers are timing closure and verification, and large FPGA designs require better planning toward achieving the desired results and the appropriate tools to help overcome this challenge.

The FPGA industry has been gearing up to address the timing closure needs of large complex designs. As FPGA designs get bigger, traditional FPGA tools with push-button capabilities will not solve critical timing closure problems. Many FPGA vendors have attempted to create tools to cover all aspects of FPGA design themselves, using a combination of features within their toolset to help users identify and fix timing issues with a minimum number of iterations.

Timing Issues

Timing analysis capabilities are part of most FPGA design software. FPGA vendors have managed to build fairly sophisticated timing analysis engines into their software tools. Designers now rely on static timing analysis tools provided by the FPGA vendor rather than any other EDA tool vendor. Designers can quickly identify timing violations and trace them all the way to the source. Xilinx, Altera and Actel provide cross-probing methods to examine paths between the timing analysis tool and the floor planner. This cross-probing capability enables designers to get a better understanding of issues that prevent them from achieving timing closure.

A modular flow is a familiar technique used by ASIC designers to obtain predictable performance and localize design changes. This technique has found its way into FPGA tools in different forms. Almost every FPGA vendor now offers a floorplanner, which, when combined with physical design features to lock down blocks of design, enables designers to predict and fix performance of known modules in a design. These tools help users fix portions of the design that have been laid out, to incrementally improve timing issues. The FPGA vendor’s physical design tools handle only the changed portions of the design through incremental placement and routing to improve performance.

Synthesis tool vendors also offer modular design capabilities—Mentor Graphics through a block flow and Synplicity through its Multipoint synthesis—which help designers optimize different independent sections of the design. These tools offer the capability to re-optimize critical regions of the design and apply performance improvement techniques through a variety of means, including register retiming and logic replication. ASIC designers accustomed to working with multiple EDA tools to perform different tasks through scripts can do the same with the FPGA tools. Figure 2 describes a typical iterative design flow between front-end tools, the physical implementation and the back-end tools. During multiple iterative runs, information exchange between the third-party and FPGA vendor tools becomes essential for quick timing closure.

FPGA designers have been using simulation, including back-annotated timing simulations, to verify design functionality. Recently, EDA tool vendors have introduced FPGA formal verification tools. In addition to these software methods, there are a variety of in-system debugging methods and devices that are available to validate the design on an actual device. Some of these debugging devices operate at full design speed and tap out the captured data through boundary scan logic for analysis.

New Technologies for FPGAs

As the geometries shrink, it is increasingly difficult for synthesis tools to optimize and map designs on the same critical regions as the ones appearing after layout on the FPGA. The current synthesis engines rely on wire load models and have no information on the physical layout of the design on the FPGA. There is a greater scope for improving design performance if the physical layout can be considered during synthesis or re-synthesis.

Physical synthesis has been in use in the ASIC world and is now available to FPGA designers with such tools as Synplicity’s Amplify Physical Optimizer, Mentor Graphics’ Precision Physical and Magma Design Automation’s Palace. The Amplify Physical Optimizer and Precision Physical tools synthesize RTL designs whereas Palace works on mapped netlists to optimize for improved performance. The leading FPGA vendors who possess synthesis technology are also announcing tightly integrated physical synthesis features within their design tools.

Large designs, even for FPGAs, involve extremely long design iteration times. To minimize the number of design iterations and to spot timing closure issues, designers need tools that identify problems in the early stages. Moreover, tools that help analyze the design at a higher level help designers quickly detect and resolve design problems. This technique, known as "design planning," is now available for FPGAs through EDA start-up Hier Design. Design planning and physical synthesis are bringing the front-end and back-end design systems together, and these capabilities are likely to be absorbed by tools on either side of the design flow as shown in Figure 2.

FPGA tools have progressed considerably during the last few years with the rapid adoption of ASIC-like technologies into FPGA flows. The readiness of the FPGA and EDA tool vendors to deliver these capabilities to FPGA users will help ASIC designers adapt to FPGA tool suites more easily than before. FPGA design tools will grow richer, driven by the ease of use requirements of FPGA designers. As FPGA devices become more customized to address-specific market segments, new tools will emerge to address high-speed board and system design needs. The EDA tool vendor and the FPGA communities have made considerable progress in their collaboration, and they will continue to work together to address the challenges that lie ahead to create smoother design flows between their tools.

Actel
Mountain View, CA. 
(650) 318-4200. 
[www.actel.com].